diff options
| author | Furquan Shaikh <furquan@google.com> | 2021-04-11 12:06:26 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-18 20:41:04 +0000 |
| commit | e206e2e7ff91ec9ebe7789eab37510874de9edf4 (patch) | |
| tree | 67b2f3643682c919f5e5c4b7a0f2505aa1b5ce92 /src/mainboard/google/drallion | |
| parent | e79431288209f239600874b8f0c45a9490fa0ed6 (diff) | |
soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
done") introduced a workaround in coreboot for `soc/intel/cannonlake`
platforms to save and restore GPIO configuration performed by
mainboard across call to FSP Silicon Init (FSP-S). This workaround was
required because FSP-S was configuring GPIOs differently than
mainboard resulting in boot and runtime issues because of
misconfigured GPIOs.
This issue has since been fixed in FSP (verified with FSP v1263 on
hatch). However, there were still 4 boards in coreboot using
`cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u
and system76/lemp9 were tested to ensure that this workaround is no
longer required.
This change drops the workaround using `cnl_configure_pads()` and
updates all mainboards to use `gpio_configure_pads()` instead.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Tested-by: Angel Pons <th3fanbus@gmail.com>
(Tested purism/librem_cnl)
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
(Tested clevo/cml-u which is similar to system76/lemp9)
Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion')
| -rw-r--r-- | src/mainboard/google/drallion/ramstage.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index ceba219ecf..d44c7b19d3 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <smbios.h> -#include <soc/gpio.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -30,7 +29,7 @@ static void mainboard_init(void *chip_info) size_t num_gpios; gpio_table = variant_gpio_table(&num_gpios); - cnl_configure_pads(gpio_table, num_gpios); + gpio_configure_pads(gpio_table, num_gpios); } static void mainboard_enable(struct device *dev) |