diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2018-07-11 12:07:51 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-27 09:00:49 +0000 |
commit | 3a14338625d6ae7c6c4e8ee0b1e9be285593b3a6 (patch) | |
tree | 75e78040495541302dbc483bd87a36d51981b8d3 /src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb | |
parent | 13415333fedada138515a986afab799ca05a785f (diff) |
mb/google/dragonegg: Add initial mainboard code support
This patch includes support for both ICL ES0 and ES1 samples.
Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md
TEST=Able to build and boot dragonegg.
Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb')
-rw-r--r-- | src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb | 281 |
1 files changed, 281 insertions, 0 deletions
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..56d923e0c1 --- /dev/null +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -0,0 +1,281 @@ +chip soc/intel/icelake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "PMC_GPP_B" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_C" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "ScsEmmcHs400Enabled" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_LONG(OC2)" # Type-C Port 3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" + + # Enable Pch iSCLK + register "pch_isclk" = "1" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "PrmrrSize" = "0x10000000" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "7" + register "PcieClkSrcUsage[2]" = "8" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + # Enable S0ix + register "s0ix_enable" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Right"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear Left"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Front Left"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Right"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Front Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 14.2 off end # PMC SRAM + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 off end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW0_06" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 off end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end + end + end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end |