mb/google/dragonegg: Add initial mainboard code support

This patch includes support for both ICL ES0 and ES1 samples.

Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md

TEST=Able to build and boot dragonegg.

Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

7 files changed, 638 insertions, 0 deletions

diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000000..22736b9001
--- /dev/null
+++ b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000000..56d923e0c1
--- /dev/null
+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
@@ -0,0 +1,281 @@
+chip soc/intel/icelake
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "PMC_GPP_B"
+	register "gpe0_dw1" = "PMC_GPP_D"
+	register "gpe0_dw2" = "PMC_GPP_C"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Enabled"
+	register "SmbusEnable" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 1
+	register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 2
+	register "usb2_ports[2]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 3
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# Type-A
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Camera
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
+
+	# Enable Pch iSCLK
+	register "pch_isclk" = "1"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	register "PrmrrSize" = "0x10000000"
+
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[3]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpEnable[6]" = "1"
+	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpEnable[9]" = "1"
+	register "PcieRpEnable[10]" = "1"
+	register "PcieRpEnable[11]" = "1"
+	register "PcieRpEnable[12]" = "1"
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpEnable[15]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "0x80"
+	register "PcieClkSrcUsage[1]" = "7"
+	register "PcieClkSrcUsage[2]" = "8"
+	register "PcieClkSrcUsage[3]" = "0x80"
+	register "PcieClkSrcUsage[4]" = "0x80"
+	register "PcieClkSrcUsage[5]" = "0x80"
+	register "PcieClkSrcUsage[6]" = "0x80"
+	register "PcieClkSrcUsage[7]" = "0x80"
+	register "PcieClkSrcUsage[8]" = "0x80"
+	register "PcieClkSrcUsage[9]" = "0x80"
+	register "PcieClkSrcUsage[10]" = "0x80"
+	register "PcieClkSrcUsage[11]" = "0x80"
+	register "PcieClkSrcUsage[12]" = "0x80"
+	register "PcieClkSrcUsage[13]" = "0x80"
+	register "PcieClkSrcUsage[14]" = "0x80"
+	register "PcieClkSrcUsage[15]" = "0x80"
+
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "SerialIoGSpiMode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoGSpiCsMode" = "{
+		[PchSerialIoIndexGSPI0] = 1,
+		[PchSerialIoIndexGSPI1] = 1,
+		[PchSerialIoIndexGSPI2] = 1,
+	}"
+
+	register "SerialIoGSpiCsState" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	# Enable S0ix
+	register "s0ix_enable" = "0"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#+-------------------+---------------------------+
+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+	}"
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 off  end # SA Thermal device
+		device pci 12.0 off  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Right""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device usb 2.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Rear Left""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device usb 2.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Front Left""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device usb 2.2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Right""
+						register "type" = "UPC_TYPE_USB3_A"
+						device usb 2.3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Right""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device usb 3.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Rear Left""
+						register "type" = "UPC_TYPE_USB3_A"
+						device usb 3.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Front Right""
+						register "type" = "UPC_TYPE_USB3_A"
+						device usb 3.2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Right""
+						register "type" = "UPC_TYPE_USB3_A"
+						device usb 3.3 on end
+					end
+				end
+			end
+		end # USB xHCI
+		device pci 14.2 off end # PMC SRAM
+		device pci 14.1 off end # USB xDCI (OTG)
+		chip drivers/intel/wifi
+			register "wake" = "GPE0_PME_B0"
+			device pci 14.3 on  end # CNVi wifi
+		end
+		device pci 14.5 on  end # SDCard
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 on  end # I2C #2
+		device pci 15.3 on  end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 off  end # SATA
+		device pci 19.0 on  end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 on  end # eMMC
+		device pci 1c.0 on
+			chip drivers/intel/wifi
+				register "wake" = "GPE0_DW0_06"
+				device pci 00.0 on end
+			end
+		end # PCI Express Port 1 x4 SLOT1
+		device pci 1c.4 off  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on end # LPC Interface
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 off  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c
new file mode 100644
index 0000000000..f1752b9b4d
--- /dev/null
+++ b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+/* I2S2_SCLK */		PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
+/* I2S2_RXD */		PAD_CFG_GPI(GPP_A10, NONE, PLTRST),
+/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+/* USB_OC_ODL */		PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+/* WLAN_PCIE_WAKE_L */	PAD_CFG_GPI_SCI(GPP_B6, NONE, DEEP, EDGE_SINGLE,
+			INVERT),
+/* PCH_WP_OD */	PAD_CFG_GPI(GPP_B7, UP_20K, DEEP),
+/* PCH_SPI_FPMCU_F7_CS_L */	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
+/* PEN_INT_ODL */	PAD_CFG_GPI(GPP_C2, NONE, PLTRST),
+/* GPP_C5_STRAP */	PAD_CFG_GPO(GPP_C5, 1, DEEP),
+/* TCH_INT_ODL */			PAD_CFG_GPI(GPP_C10, NONE, PLTRST),
+/* TCH_RST_ODL */		PAD_CFG_GPO(GPP_C11, 0, PLTRST),
+/* M2_SHUTDOWN+L */		PAD_CFG_GPO(GPP_C12, 1, PLTRST),
+/* M2_RESET_L */		PAD_CFG_GPO(GPP_C13, 1, PLTRST),
+/* M2_INT_L */			PAD_CFG_GPI(GPP_C14, NONE, PLTRST),
+/* HP_INT_L */			PAD_CFG_GPI(GPP_C15, NONE, PLTRST),
+/* PCH_DEV_INT_ODL */			PAD_CFG_GPI(GPP_C22, NONE, PLTRST),
+/* PCH_DEV_RESET_L */		PAD_CFG_GPO(GPP_C23, 0, PLTRST),
+/* PCI_NVME_CLKREQ_ODL */		PAD_CFG_NF(GPP_D7, UP_20K, PWROK, NF1),
+/* H1_PCH_INT_ODL */	PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL,
+		INVERT),
+/* GPP_E6_STRAP */		PAD_CFG_GPO(GPP_E6, 1, DEEP),
+/* USB_C0_SBU_1_DC */		PAD_CFG_GPO(GPP_E22, 1, PLTRST),
+/* USB_C0_SBU_2_DC */	PAD_CFG_GPO(GPP_E23, 0, DEEP),
+/* CNV_RF_RESET_N */		PAD_CFG_NF(GPP_F4, DN_20K, PWROK, NF1),
+/* CNV_CLKREQ0 */		PAD_CFG_NF(GPP_F5, DN_20K, PWROK, NF2),
+/* SD_CD# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, UP_20K, DEEP),
+/* SD_WP */		PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
+/* PCH_MEM_STRAP0 */		PAD_CFG_GPI(GPP_H12, DN_20K, PLTRST),
+/* PCH_MEM_STRAP1 */		PAD_CFG_GPI(GPP_H13, DN_20K, PLTRST),
+/* PCH_MEM_STRAP2 */		PAD_CFG_GPI(GPP_H14, DN_20K, PLTRST),
+/* PCH_MEM_STRAP3 */		PAD_CFG_GPI(GPP_H15, DN_20K, PLTRST),
+};
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+/* PCH_WP_OD */	PAD_CFG_GPI(GPP_B7, UP_20K, DEEP),
+/* GSPI0_CS# */	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+/* GSPI0_CLK */	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+/* GSPI0_MISO */	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+/* GSPI0_MOSI */	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+/* H1_PCH_INT_ODL */	PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL,
+		INVERT),
+};
+
+const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *__attribute__((weak))
+	variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(39, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000000..7a2ec19a65
--- /dev/null
+++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#include <variant/gpio.h>
+
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or
+ * mode change event.
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+
+#define EC_ENABLE_MKBP_DEVICE	/* Enable cros_ec_keyb device */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..99bbb71333
--- /dev/null
+++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW	GPP_B8
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP	GPP_B7
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE		GPE0_LAN_WAK
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0	GPP_H12
+#define GPIO_MEM_CONFIG_1	GPP_H13
+#define GPIO_MEM_CONFIG_2	GPP_H14
+#define GPIO_MEM_CONFIG_3	GPP_H15
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..37a7c053b7
--- /dev/null
+++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+struct lpddr4_config {
+	const void *dq_map;
+	size_t dq_map_size;
+	const void *dqs_map;
+	size_t dqs_map_size;
+	const void *rcomp_resistor;
+	size_t rcomp_resistor_size;
+	const void *rcomp_target;
+	size_t rcomp_target_size;
+};
+void variant_memory_params(struct lpddr4_config *mem_config);
+int variant_memory_sku(void);
+#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/memory.c b/src/mainboard/google/dragonegg/variants/baseboard/memory.c
new file mode 100644
index 0000000000..c7d579b1a9
--- /dev/null
+++ b/src/mainboard/google/dragonegg/variants/baseboard/memory.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <intelblocks/mp_init.h>
+#include <variant/gpio.h>
+
+/* DQ byte map */
+static const u8 dq_map[][12] = {
+	{ 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
+	  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	{ 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
+	  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+};
+
+/* DQS CPU<>DRAM map */
+static const u8 dqs_map[][8] = {
+	{ 0, 1, 2, 3, 4, 5, 6, 7 },
+	{ 0, 1, 2, 3, 5, 4, 7, 6 },
+};
+
+/* Rcomp resistor */
+static const u16 rcomp_resistor[] = { 100, 100, 100 };
+
+/*
+ * get processor id using cpuid eax=1
+ * return value will be in EAX register
+ */
+static uint32_t get_cpuid(void)
+{
+	struct cpuid_result cpuidr;
+
+	cpuidr = cpuid(1);
+
+	return cpuidr.eax;
+}
+
+void __weak variant_memory_params(struct lpddr4_config *mem_config)
+{
+	/* Rcomp target */
+	static const u16 rcomp_target_es0[] = { 80, 40, 40, 40, 30 };
+	static const u16 rcomp_target_es1[] = { 60, 20, 20, 20, 20 };
+
+	mem_config->dq_map = dq_map;
+	mem_config->dq_map_size = sizeof(dq_map);
+	mem_config->dqs_map = dqs_map;
+	mem_config->dqs_map_size = sizeof(dqs_map);
+	mem_config->rcomp_resistor = rcomp_resistor;
+	mem_config->rcomp_resistor_size = sizeof(rcomp_resistor);
+	if (get_cpuid() == CPUID_ICELAKE_A0) {
+		mem_config->rcomp_target = rcomp_target_es0;
+		mem_config->rcomp_target_size = sizeof(rcomp_target_es0);
+	} else {
+		mem_config->rcomp_target = rcomp_target_es1;
+		mem_config->rcomp_target_size = sizeof(rcomp_target_es1);
+	}
+}
+
+int __weak variant_memory_sku(void)
+{
+	gpio_t spd_gpios[] = {
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}