diff options
| author | stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> | 2021-07-29 17:50:36 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-31 09:14:50 +0000 |
| commit | 0f80767ee1f0fccd6116accda1eb53770b7ddbc1 (patch) | |
| tree | f7e3d309f46e5c5193ef9215e0642b1bfb2120e2 /src/mainboard/google/dedede/variants/boten | |
| parent | f80e6d6f567b8f47e32b3f54b846802825510bf9 (diff) | |
mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0ms
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.
BUG=b:187801363
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/boten')
| -rw-r--r-- | src/mainboard/google/dedede/variants/boten/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 8c68f7eea6..d310f91f02 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -80,6 +80,9 @@ chip soc/intel/jasperlake register "SlowSlewRate" = "SlewRateFastBy8" register "FastPkgCRampDisable" = "1" + # Set xHCI LFPS period sampling off time to 0 ms + register "xhci_lfps_sampling_offtime_ms" = "0" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf |