From 0f80767ee1f0fccd6116accda1eb53770b7ddbc1 Mon Sep 17 00:00:00 2001 From: "stanley.wu" Date: Thu, 29 Jul 2021 17:50:36 +0800 Subject: mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0ms LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:187801363 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: stanley.wu Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Ben Kao --- src/mainboard/google/dedede/variants/boten/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/dedede/variants/boten') diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 8c68f7eea6..d310f91f02 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -80,6 +80,9 @@ chip soc/intel/jasperlake register "SlowSlewRate" = "SlewRateFastBy8" register "FastPkgCRampDisable" = "1" + # Set xHCI LFPS period sampling off time to 0 ms + register "xhci_lfps_sampling_offtime_ms" = "0" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- cgit v1.2.3