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authorChia-Ling Hou <chia-ling.hou@intel.com>2023-06-07 16:53:00 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-06-23 15:22:45 +0000
commitb5a032859aec1449b46eed60a6c6aeb9147e45a7 (patch)
tree1fe057507bc9193485619a060990ebddc5ba8f9c /src/mainboard/google/dedede/variants/blipper
parent3dedfcbbd472fe569e06e8454db77fa8915a0a2f (diff)
soc/intel/jasperlake: Add per-SKU power limits
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Super Ni <super.ni@intel.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/blipper')
-rw-r--r--src/mainboard/google/dedede/variants/blipper/overridetree.cb5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
index 518b962fd0..a507dd1461 100644
--- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
@@ -59,11 +59,6 @@ chip soc/intel/jasperlake
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
- register "power_limits_config" = "{
- .tdp_pl1_override = 6,
- .tdp_pl2_override = 20,
- }"
-
register "tcc_offset" = "10" # TCC of 95C
# Enable Acoustic noise mitigation and set slew rate to 1/8