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authorTeddy Shih <teddyshih@ami.corp-partner.google.com>2022-06-08 14:02:46 +0800
committerMartin L Roth <gaumless@tutanota.com>2022-06-12 22:43:12 +0000
commitcee275fd5c216f56f77c6d52f01fa91c1bfc0447 (patch)
tree82d2a423528f878c35f704c92e9fcddebc3a2b3e /src/mainboard/google/dedede/variants/beadrix/overridetree.cb
parent2c102232e8f74cff55e1ee75f785781ab27111dd (diff)
mb/google/dedede/beadrix: Update probe daughter LTE mainboard SAR
Update FW_CONFIG probe for daughter board LTE and mainboard SAR according to beadrix schematics. BRANCH=dedede BUG=b:226910787, b:213549229, b:233983127 TEST=on beadrix, validated by beadrix LTE working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I126a1c548b6314acc0749fcfbdffd8f482c4f46c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/beadrix/overridetree.cb')
-rw-r--r--src/mainboard/google/dedede/variants/beadrix/overridetree.cb6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
index 909558323e..82677a2956 100644
--- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
@@ -121,7 +121,7 @@ chip soc/intel/jasperlake
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
register "enable_delay_ms" = "20"
device usb 3.3 on
- probe LTE LTE_PRESENT
+ probe DB_PORTS DB_PORTS_1C_LTE
end
end
end
@@ -218,7 +218,9 @@ chip soc/intel/jasperlake
register "reg_irq_cfg0" = "0x00"
register "reg_irq_cfg1" = "0x80"
register "reg_irq_cfg2" = "0x00"
- device i2c 28 on end
+ device i2c 28 on
+ probe DB_PORTS DB_PORTS_1C_LTE
+ end
end
end # I2C 5
device pci 1f.3 on