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authorElyes Haouas <ehaouas@noos.fr>2024-03-23 15:29:37 +0100
committerElyes Haouas <ehaouas@noos.fr>2024-03-30 07:45:40 +0000
commitc55765d6818534236338539101630448f00d1595 (patch)
treef6e54d36cc3e7ce01e7677b8e234bbd3b4886f7e /src/mainboard/google/cyan/variants/kefka
parent4709d7c028cccfc4b47b03053965d459b320ad25 (diff)
mb/google: Remove blank lines before '}' and after '{'
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/kefka')
-rw-r--r--src/mainboard/google/cyan/variants/kefka/ramstage.c1
-rw-r--r--src/mainboard/google/cyan/variants/kefka/romstage.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c
index e1fd33aecf..96d53c25ef 100644
--- a/src/mainboard/google/cyan/variants/kefka/ramstage.c
+++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c
@@ -5,7 +5,6 @@
void board_silicon_USB2_override(SILICON_INIT_UPD *params)
{
if (SocStepping() >= SocD0) {
-
//Follow Intel recommendation to set
//BSW D-stepping PERPORTRXISET 2 (low strength)
params->D0Usb2Port0PerPortRXISet = 2;
diff --git a/src/mainboard/google/cyan/variants/kefka/romstage.c b/src/mainboard/google/cyan/variants/kefka/romstage.c
index 9492b84b51..d5e88830af 100644
--- a/src/mainboard/google/cyan/variants/kefka/romstage.c
+++ b/src/mainboard/google/cyan/variants/kefka/romstage.c
@@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
* RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107
*/
if (ram_id == 2 || ram_id == 3) {
-
/*
* For new micron part, it requires read/receive
* enable training before sending cmds to get MR8.