diff options
Diffstat (limited to 'src/mainboard/google/cyan/variants/kefka')
| -rw-r--r-- | src/mainboard/google/cyan/variants/kefka/ramstage.c | 1 | ||||
| -rw-r--r-- | src/mainboard/google/cyan/variants/kefka/romstage.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c index e1fd33aecf..96d53c25ef 100644 --- a/src/mainboard/google/cyan/variants/kefka/ramstage.c +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -5,7 +5,6 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { - //Follow Intel recommendation to set //BSW D-stepping PERPORTRXISET 2 (low strength) params->D0Usb2Port0PerPortRXISet = 2; diff --git a/src/mainboard/google/cyan/variants/kefka/romstage.c b/src/mainboard/google/cyan/variants/kefka/romstage.c index 9492b84b51..d5e88830af 100644 --- a/src/mainboard/google/cyan/variants/kefka/romstage.c +++ b/src/mainboard/google/cyan/variants/kefka/romstage.c @@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) * RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 3) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. |