diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-26 06:10:18 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-09-21 17:31:51 +0000 |
commit | 3b498a0b533713d8d158611863d090ac68116c4d (patch) | |
tree | b13f0688c00d01870969a805ee4bc5fb5bfcb6b2 /src/mainboard/google/cyan/variants/celes/ramstage.c | |
parent | 6fd2e0e088f678f24554a3e29c25f9d030f2cb66 (diff) |
google/celes: add new board as variant of cyan baseboard
Add support for google/celes (Samsung Chromebook 3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new celes variant
- Add new trackpad I2C device to the baseboard for potential
reuse by other variants
Sourced from Chromium branch firmware-celes-7287.92.B,
commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/celes/ramstage.c')
-rw-r--r-- | src/mainboard/google/cyan/variants/celes/ramstage.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c new file mode 100644 index 0000000000..ac5cd3b0de --- /dev/null +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + if (SocStepping() >= SocD0) { + + params->Usb2Port0PerPortPeTxiSet = 7; + params->Usb2Port0PerPortTxiSet = 0; + params->Usb2Port0IUsbTxEmphasisEn = 3; + params->Usb2Port0PerPortTxPeHalf = 1; + + params->Usb2Port1PerPortPeTxiSet = 7; + params->Usb2Port1PerPortTxiSet = 0; + params->Usb2Port1IUsbTxEmphasisEn = 3; + params->Usb2Port1PerPortTxPeHalf = 1; + + params->Usb2Port2PerPortPeTxiSet = 7; + params->Usb2Port2PerPortTxiSet = 6; + params->Usb2Port2IUsbTxEmphasisEn = 3; + params->Usb2Port2PerPortTxPeHalf = 1; + + params->Usb2Port3PerPortPeTxiSet = 7; + params->Usb2Port3PerPortTxiSet = 6; + params->Usb2Port3IUsbTxEmphasisEn = 3; + params->Usb2Port3PerPortTxPeHalf = 1; + + params->Usb2Port4PerPortPeTxiSet = 7; + params->Usb2Port4PerPortTxiSet = 6; + params->Usb2Port4IUsbTxEmphasisEn = 3; + params->Usb2Port4PerPortTxPeHalf = 1; + } +} |