google/celes: add new board as variant of cyan baseboard

Add support for google/celes (Samsung Chromebook 3) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new celes variant
- Add new trackpad I2C device to the baseboard for potential
reuse by other variants

Sourced from Chromium branch firmware-celes-7287.92.B,
commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""

Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

9 files changed, 730 insertions, 0 deletions

diff --git a/src/mainboard/google/cyan/variants/celes/Makefile.inc b/src/mainboard/google/cyan/variants/celes/Makefile.inc
new file mode 100644
index 0000000000..0fcc9add0b
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/Makefile.inc
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE    # Index0
+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF   # Index1
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/cyan/variants/celes/board_info.txt b/src/mainboard/google/cyan/variants/celes/board_info.txt
new file mode 100644
index 0000000000..97ddfe9825
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Celes
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb
new file mode 100644
index 0000000000..84edd74126
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb
@@ -0,0 +1,150 @@
+chip soc/intel/braswell
+
+	############################################################
+	# Set the parameters for MemoryInit
+	############################################################
+
+	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
+
+	register "PcdMrcInitMmioSize" = "0x0800"
+	register "PcdMrcInitSpdAddr1" = "0xa0"
+	register "PcdMrcInitSpdAddr2" = "0xa2"
+	register "PcdIgdDvmt50PreAlloc" = "1"
+	register "PcdApertureSize" = "2"
+	register "PcdGttSize" = "1"
+	register "PcdDvfsEnable" = "1"
+	register "PcdCaMirrorEn" = "1"
+
+	############################################################
+	# Set the parameters for SiliconInit
+	############################################################
+
+	register "PcdSdcardMode" = "PCH_ACPI_MODE"
+	register "PcdEnableHsuart0" = "0"
+	register "PcdEnableHsuart1" = "1"
+	register "PcdEnableAzalia" = "1"
+	register "PcdEnableXhci" = "1"
+	register "PcdEnableLpe" = "1"
+	register "PcdEnableDma0" = "1"
+	register "PcdEnableDma1" = "1"
+	register "PcdEnableI2C0" = "0"
+	register "PcdEnableI2C1" = "1"
+	register "PcdEnableI2C2" = "0"
+	register "PcdEnableI2C3" = "0"
+	register "PcdEnableI2C4" = "1"
+	register "PcdEnableI2C5" = "1"
+	register "PcdEnableI2C6" = "0"
+	register "PunitPwrConfigDisable" = "0"	# Enable SVID
+	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
+	register "PcdEmmcMode" = "PCH_ACPI_MODE"
+	register "PcdUsb3ClkSsc" = "1"
+	register "PcdDispClkSsc" = "1"
+	register "PcdSataClkSsc" = "1"
+	register "PcdEnableSata" = "0"		# Disable SATA
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "5"
+	register "Usb2Port0IUsbTxEmphasisEn" = "2"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "3"
+	register "Usb2Port1IUsbTxEmphasisEn" = "2"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "3"
+	register "Usb2Port2IUsbTxEmphasisEn" = "2"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "3"
+	register "Usb2Port3IUsbTxEmphasisEn" = "2"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "3"
+	register "Usb2Port4IUsbTxEmphasisEn" = "2"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
+	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
+	register "PcdSataInterfaceSpeed" = "3"
+	register "PcdPchSsicEnable" = "0"
+	register "PcdPchUsbHsicPort" = "0"
+	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
+	register "PMIC_I2CBus" = "1"
+	register "ISPEnable" = "0"		# Disable IUNIT
+	register "ISPPciDevConfig" = "3"
+	register "PcdSdDetectChk" = "0"		# Disable SD card detect
+	# Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
+	register "D0Usb2Port0PerPortRXISet" = "2"
+	register "D0Usb2Port1PerPortRXISet" = "2"
+	register "D0Usb2Port2PerPortRXISet" = "2"
+	register "D0Usb2Port3PerPortRXISet" = "2"
+	register "D0Usb2Port4PerPortRXISet" = "2"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
+
+	# Enable devices in ACPI mode
+	register "lpss_acpi_mode" = "1"
+	register "emmc_acpi_mode" = "1"
+	register "sd_acpi_mode" = "1"
+	register "lpe_acpi_mode" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+					# EDS Table 24-4, Figure 24-5
+		device pci 00.0 on end	# 8086 2280 - SoC transaction router
+		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
+		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
+		device pci 0b.0 on end	# 8086 22dc - ?
+		device pci 10.0 on end	# 8086 2294 - MMC Port
+		device pci 11.0 off end	# 8086 0F15 - SDIO Port
+		device pci 12.0 on end	# 8086 0F16 - SD Port
+		device pci 13.0 off end	# 8086 22a3 - Sata controller
+		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
+		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
+		device pci 16.0 off end	# 8086 22b7 - USB device
+		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
+		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1
+		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
+		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
+		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
+		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
+		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
+		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
+		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
+		device pci 1b.0 on end	# 8086 0F04 - HD Audio
+		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
+		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
+		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
+		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
+		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
+		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
+		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
+		device pci 1e.3 on end	# 8086 228a -   HSUART 1
+		device pci 1e.4 off end	# 8086 228c -   HSUART 2
+		device pci 1e.5 on end	# 8086 228e -   SPI 1
+		device pci 1e.6 off end	# 8086 2290 -   SPI 2
+		device pci 1e.7 off end	# 8086 22ac -   SPI 3
+		device pci 1f.0 on	# 8086 229c - LPC bridge
+			chip drivers/pc80/tpm
+				# Rising edge interrupt
+				register "irq_polarity" = "2"
+				device pnp 0c31.0 on
+					irq 0x70 = 10
+				end
+			end
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c
new file mode 100644
index 0000000000..9f6ae87be5
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/gpio.c
@@ -0,0 +1,262 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard/google/cyan/irqroute.h>
+#include <soc/gpio.h>
+#include <stdlib.h>
+
+/* South East Community */
+static const struct soc_gpio_map gpse_gpio_map[] = {
+	Native_M1,/* MF_PLT_CLK0 */
+	GPIO_NC, /* 01 PWM1 */
+	GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
+	GPIO_NC, /* 03 MF_PLT_CLK4 */
+	GPIO_NC, /* 04 MF_PLT_CLK3 */
+	GPIO_NC, /* PWM0 05 */
+	GPIO_NC, /* 06 MF_PLT_CLK5 */
+	GPIO_NC, /* 07 MF_PLT_CLK2 */
+	GPIO_NC, /* 15 SDMMC2_D3_CD_B */
+	Native_M1, /* 16 SDMMC1_CLK */
+	NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
+	GPIO_NC, /* 18 SDMMC2_D1 */
+	GPIO_NC, /* 19 SDMMC2_CLK */
+	NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
+	GPIO_NC, /* 21 SDMMC2_D2 */
+	GPIO_NC, /* 22 SDMMC2_CMD  */
+	NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
+	NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
+	GPIO_NC, /* 25 SDMMC2_D0 */
+	NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
+	NATIVE_PU20K(1), /* 30 SDMMC3_D1 */
+	Native_M1, /* 31 SDMMC3_CLK */
+	NATIVE_PU20K(1), /* 32 SDMMC3_D3 */
+	NATIVE_PU20K(1), /* 33 SDMMC3_D2 */
+	NATIVE_PU20K(1), /* 34 SDMMC3_CMD */
+	NATIVE_PU20K(1), /* 35 SDMMC3_D0 */
+	NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
+	NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */
+	NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
+	Native_M1, /* 48 LPC_FRAMEB */
+	Native_M1, /* 49 MF_LPC_CLKOUT1 */
+	NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
+	Native_M1, /* 51 MF_LPC_CLKOUT0 */
+	NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
+	Native_M1,/* SPI1_MISO */
+	Native_M1, /* 61 SPI1_CS0_B */
+	Native_M1, /* SPI1_CLK */
+	NATIVE_PU20K(1), /* 63 MMC1_D6 */
+	Native_M1, /* 62 SPI1_MOSI */
+	NATIVE_PU20K(1), /* 65 MMC1_D5 */
+	GPIO_NC, /* SPI1_CS1_B  66 */
+	NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
+	NATIVE_PU20K(1), /* 68 MMC1_D7 */
+	GPIO_NC, /* 69 MMC1_RCLK */
+	Native_M1, /* 75  GPO USB_OC1_B */
+	Native_M1, /* 76  PMU_RESETBUTTON_B */
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	/* GPIO_ALERT 77   */
+	Native_M1, /* 78  SDMMC3_PWR_EN_B */
+	GPIO_NC, /* 79  GPI ILB_SERIRQ */
+	Native_M1, /* 80  USB_OC0_B */
+	GPI(trig_edge_both, L1, P_20K_H, non_maskable,
+				en_edge_detect, NA , NA),
+	/* 81  SDMMC3_CD_B */
+	GPIO_NC,  /* 82  spkr	 asummed gpio number */
+	Native_M1, /* 83 SUSPWRDNACK */
+	SPARE_PIN,/* 84 spare pin */
+	Native_M1, /* 85 SDMMC3_1P8_EN */
+	GPIO_END
+};
+
+
+/* South West Community */
+static const struct soc_gpio_map  gpsw_gpio_map[] = {
+	GPIO_NC, /* 00 FST_SPI_D2 */
+	Native_M1, /* 01 FST_SPI_D0 */
+	Native_M1, /* 02 FST_SPI_CLK */
+	GPIO_NC, /* 03 FST_SPI_D3 */
+	GPIO_NC, /* GPO FST_SPI_CS1_B */
+	Native_M1, /* 05 FST_SPI_D1 */
+	Native_M1, /* 06 FST_SPI_CS0_B */
+	GPIO_NC, /* 07 FST_SPI_CS2_B */
+	GPIO_NC, /* 15 UART1_RTS_B */
+	Native_M2, /* 16 UART1_RXD */
+	GPIO_NC, /* 17 UART2_RXD */
+	GPIO_NC, /* 18 UART1_CTS_B */
+	GPIO_NC, /* 19 UART2_RTS_B */
+	Native_M2, /* 20 UART1_TXD */
+	GPIO_NC, /* 21 UART2_TXD */
+	GPIO_NC, /* 22 UART2_CTS_B */
+	GPIO_NC, /* 30 MF_HDA_CLK */
+	GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */
+	GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */
+	GPIO_NC, /* 33 MF_HDA_SDO */
+	GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 34 MF_HDA_DOCKRSTB */
+	GPIO_NC, /* 35 MF_HDA_SYNC */
+	GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
+	GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 37 MF_HDA_DOCKENB */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
+	GPIO_NC, /* 49 I2C_NFC_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */
+	GPIO_NC, /* 52 I2C_NFC_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */
+	GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/
+	NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 66  I2C2_SCL */
+	GPIO_INPUT_NO_PULL,/* 67  I2C3_SCL,RAMID1 */
+	GPIO_OUT_HIGH, /* 75 SATA_GP0 */
+	GPIO_NC, /* 76 GPI SATA_GP1 */
+	GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */
+	GPIO_NC, /* 78 SATA_GP2 */
+	GPIO_NC, /* 79 MF_SMB_ALERTB */
+	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
+	GPIO_NC, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	GPIO_NC, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
+	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
+	Native_M1, /* 90 PCIE_CLKREQ0B */
+	GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
+	Native_M1, /* 92 GP_SSP_2_CLK */
+	NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
+	Native_M1, /* 94 GP_SSP_2_RXD */
+	GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
+	Native_M1, /* 96 GP_SSP_2_FS */
+	NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
+	GPIO_END
+};
+
+
+/* North Community */
+static const struct soc_gpio_map  gpn_gpio_map[] = {
+	GPIO_NC, /* 00 GPIO_DFX0 */
+	GPIO_NC, /* 01 GPIO_DFX3 */
+	GPIO_NC, /* 02 GPIO_DFX7 */
+	GPIO_NC, /* 03 GPIO_DFX1 */
+	GPIO_NC, /* 04 GPIO_DFX5 */
+	GPIO_NC, /* 05 GPIO_DFX4 */
+	GPIO_NC, /* 06 GPIO_DFX8 */
+	GPIO_NC, /* 07 GPIO_DFX2 */
+	GPIO_NC, /* 08 GPIO_DFX6 */
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
+	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
+	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
+	/* 17 GPIO_SUS3 */
+	GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
+	/* 18 GPIO_SUS7 */
+	GPIO_NC,
+	/* 19 GPIO_SUS1 */
+	GPIO_NC, /* 20 GPIO_SUS5 */
+	GPIO_NC, /* 21 SEC_GPIO_SUS11 */
+	GPIO_NC, /* 22 GPIO_SUS4 */
+	GPIO_NC,
+	/* 23 SEC_GPIO_SUS8 */
+	Native_M6, /* 24 GPIO_SUS2 */
+	GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
+	Native_M1, /* 26 CX_PREQ_B */
+	GPIO_NC, /* 27 SEC_GPIO_SUS9 */
+	Native_M1, /* 30 TRST_B */
+	Native_M1, /* 31 TCK */
+	GPIO_SKIP, /* 32 PROCHOT_B */
+	GPIO_SKIP, /* 33 SVID0_DATA */
+	Native_M1, /* 34 TMS */
+	GPIO_NC, /* 35 CX_PRDY_B_2 */
+	GPIO_NC, /* 36 TDO_2 */
+	Native_M1, /* 37 CX_PRDY_B */
+	GPIO_SKIP, /* 38 SVID0_ALERT_B */
+	Native_M1, /* 39 TDO */
+	GPIO_SKIP, /* 40 SVID0_CLK */
+	Native_M1, /* 41 TDI */
+	GPIO_NC, /* 45 GP_CAMERASB05 */
+	GPIO_NC, /* 46 GP_CAMERASB02 */
+	GPIO_NC, /* 47 GP_CAMERASB08 */
+	GPIO_NC, /* 48 GP_CAMERASB00 */
+	GPIO_NC, /* 49 GP_CAMERASBO6 */
+	GPIO_NC, /* 50 GP_CAMERASB10 */
+	GPIO_NC, /* 51 GP_CAMERASB03 */
+	GPIO_NC, /* 52 GP_CAMERASB09 */
+	GPIO_NC, /* 53 GP_CAMERASB01 */
+	GPIO_NC, /* 54 GP_CAMERASB07 */
+	GPIO_NC, /* 55 GP_CAMERASB11 */
+	GPIO_NC, /* 56 GP_CAMERASB04 */
+	GPIO_NC, /* 60 PANEL0_BKLTEN */
+	GPIO_NC, /* 61 HV_DDI0_HPD */
+	NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */
+	Native_M1, /* 63 PANEL1_BKLTCTL */
+	NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */
+	GPIO_NC, /* 65 PANEL0_BKLTCTL */
+	GPIO_NC, /* 66 HV_DDI0_DDC_SDA */
+	NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */
+	NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
+	Native_M1, /* 69 PANEL1_VDDEN */
+	Native_M1, /* 70 PANEL1_BKLTEN */
+	GPIO_NC, /* 71 HV_DDI0_DDC_SCL */
+	GPIO_NC, /* 72 PANEL0_VDDEN */
+	GPIO_END
+};
+
+
+/* East Community */
+static const struct soc_gpio_map  gpe_gpio_map[] = {
+	Native_M1, /* 00 PMU_SLP_S3_B */
+	GPIO_NC, /* 01 PMU_BATLOW_B */
+	Native_M1, /* 02 SUS_STAT_B */
+	Native_M1, /* 03 PMU_SLP_S0IX_B */
+	Native_M1, /* 04 PMU_AC_PRESENT */
+	Native_M1, /* 05 PMU_PLTRST_B */
+	Native_M1, /* 06 PMU_SUSCLK */
+	GPIO_NC, /* 07 PMU_SLP_LAN_B */
+	Native_M1, /* 08 PMU_PWRBTN_B */
+	Native_M1, /* 09 PMU_SLP_S4_B */
+	NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
+	GPIO_NC, /* 11 PMU_WAKE_LAN_B */
+	GPIO_NC, /* 15 MF_GPIO_3 */
+	GPIO_NC, /* 16 MF_GPIO_7 */
+	GPIO_NC, /* 17 MF_I2C1_SCL */
+	GPIO_NC, /* 18 MF_GPIO_1 */
+	GPIO_NC, /* 19 MF_GPIO_5 */
+	GPIO_NC, /* 20 MF_GPIO_9 */
+	GPIO_NC, /* 21 MF_GPIO_0 */
+	GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4,PCH1_SPI_WP */
+	GPIO_NC, /* 23 MF_GPIO_8 */
+	GPIO_NC, /* 24 MF_GPIO_2 */
+	GPIO_NC, /* 25 MF_GPIO_6 */
+	GPIO_NC, /* 26 MF_I2C1_SDA */
+	GPIO_END
+};
+
+
+static struct soc_gpio_config gpio_config = {
+	/* BSW */
+	.north = gpn_gpio_map,
+	.southeast = gpse_gpio_map,
+	.southwest  = gpsw_gpio_map,
+	.east = gpe_gpio_map
+};
+
+struct soc_gpio_config *mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..fa2eea92d0
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2105 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"NCP15WB_CPU"
+#define DPTF_TSR0_PASSIVE	52
+#define DPTF_TSR0_CRITICAL	80
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"NCP15WB_DIMM"
+#define DPTF_TSR1_PASSIVE	55
+#define DPTF_TSR1_CRITICAL	80
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"NCP15WB_PMIC"
+#define DPTF_TSR2_PASSIVE	60
+#define DPTF_TSR2_CRITICAL	80
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		6200,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..75797f8bc4
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Matt DeVillier
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Atmel trackpad */
+#include <acpi/trackpad_atmel.asl>
+
+/* Realtek audio codec */
+#include <acpi/codec_realtek.asl>
diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h b/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h
new file mode 100644
index 0000000000..f156004f9b
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/cyan/irqroute.h>
+
+/*
+ * Calculation of gpio based irq.
+ * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
+ * Max direct irq (MAX_DIRECT_IRQ) is 114.
+ * Size of gpio banks are
+ * GPSW_SIZE = 98
+ * GPNC_SIZE = 73
+ * GPEC_SIZE = 27
+ * GPSE_SIZE = 86
+ */
+
+/* KBD: Gpio index in N bank */
+#define BOARD_I8042_GPIO_INDEX		17
+/* Audio: Gpio index in SW bank */
+#define JACK_DETECT_GPIO_INDEX		95
+/* SCI: Gpio index in N bank */
+#define BOARD_SCI_GPIO_INDEX		15
+/* Trackpad: Gpio index in N bank */
+#define BOARD_TRACKPAD_GPIO_INDEX	18
+
+#define BOARD_TRACKPAD_NAME		"trackpad"
+#define BOARD_TRACKPAD_WAKE_GPIO	ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS		5
+#define BOARD_TRACKPAD_I2C_ADDR		0x4a
+
+/* SD CARD gpio */
+#define SDCARD_CD			81
+
+#define AUDIO_CODEC_HID			"10EC5650"
+#define AUDIO_CODEC_CID			"10EC5650"
+#define AUDIO_CODEC_DDN			"RTEK Codec Controller"
+#define AUDIO_CODEC_I2C_ADDR		0x1A
+
+#endif
diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c
new file mode 100644
index 0000000000..ac5cd3b0de
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/ramstage.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+{
+	if (SocStepping() >= SocD0) {
+
+		params->Usb2Port0PerPortPeTxiSet = 7;
+		params->Usb2Port0PerPortTxiSet = 0;
+		params->Usb2Port0IUsbTxEmphasisEn = 3;
+		params->Usb2Port0PerPortTxPeHalf = 1;
+
+		params->Usb2Port1PerPortPeTxiSet = 7;
+		params->Usb2Port1PerPortTxiSet = 0;
+		params->Usb2Port1IUsbTxEmphasisEn = 3;
+		params->Usb2Port1PerPortTxPeHalf = 1;
+
+		params->Usb2Port2PerPortPeTxiSet = 7;
+		params->Usb2Port2PerPortTxiSet = 6;
+		params->Usb2Port2IUsbTxEmphasisEn = 3;
+		params->Usb2Port2PerPortTxPeHalf = 1;
+
+		params->Usb2Port3PerPortPeTxiSet = 7;
+		params->Usb2Port3PerPortTxiSet = 6;
+		params->Usb2Port3IUsbTxEmphasisEn = 3;
+		params->Usb2Port3PerPortTxPeHalf = 1;
+
+		params->Usb2Port4PerPortPeTxiSet = 7;
+		params->Usb2Port4PerPortTxiSet = 6;
+		params->Usb2Port4IUsbTxEmphasisEn = 3;
+		params->Usb2Port4PerPortTxPeHalf = 1;
+	}
+}
diff --git a/src/mainboard/google/cyan/variants/celes/spd_util.c b/src/mainboard/google/cyan/variants/celes/spd_util.c
new file mode 100644
index 0000000000..d6253368e9
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/spd_util.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2017 Matt DeVillier
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <mainboard/google/cyan/spd/spd_util.h>
+
+/*
+ * Usage of RAMID straps
+ *
+ *  RAMID1 - Single/Dual channel configuration
+ *   0 - Dual channel, 1 - Single channel
+ *
+ *  Combination of RAMID3, RAMID2, RAMID0 - Index of SPD table
+ *   Index 0 - Samsung K4E8E304EE-EGCE 1600MHz 23nm
+ *   Index 1 - Samsung K4E8E324EB-EGCF 1866MHz 20nm
+ */
+
+uint8_t get_ramid(void)
+{
+	gpio_t spd_gpios[] = {
+		GP_SW_80,	/* SATA_GP3,RAMID0 */
+		GP_SE_02,	/* MF_PLT_CLK1, RAMID2 */
+		GP_SW_64,	/* I2C3_SDA RAMID3 */
+		GP_SW_67,	/* I2C3_SCL,RAMID1 */
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+int get_variant_spd_index(int ram_id, int *dual)
+{
+	int spd_index = ram_id & 0x7;
+
+	/* Determine if single or dual channel memory system */
+	/* RAMID3 is deterministic for celes */
+	*dual = ((ram_id > 3) & 0x1) ? 0 : 1;
+
+	/* Display the RAM type */
+	printk(BIOS_DEBUG, dual ? "4GiB " : "2GiB ");
+	switch (spd_index) {
+	case 0:
+		printk(BIOS_DEBUG, "Samsung K4E8E304EE-EGCE\n");
+		break;
+	case 1:
+		printk(BIOS_DEBUG, "Samsung K4E8E324EB-EGCF\n");
+		break;
+	}
+
+	return spd_index;
+}