google/celes: add new board as variant of cyan baseboard

Add support for google/celes (Samsung Chromebook 3) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new celes variant
- Add new trackpad I2C device to the baseboard for potential
reuse by other variants

Sourced from Chromium branch firmware-celes-7287.92.B,
commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""

Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

3 files changed, 160 insertions, 0 deletions

diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..fa2eea92d0
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2105 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"NCP15WB_CPU"
+#define DPTF_TSR0_PASSIVE	52
+#define DPTF_TSR0_CRITICAL	80
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"NCP15WB_DIMM"
+#define DPTF_TSR1_PASSIVE	55
+#define DPTF_TSR1_CRITICAL	80
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"NCP15WB_PMIC"
+#define DPTF_TSR2_PASSIVE	60
+#define DPTF_TSR2_CRITICAL	80
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		6200,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..75797f8bc4
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Matt DeVillier
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Atmel trackpad */
+#include <acpi/trackpad_atmel.asl>
+
+/* Realtek audio codec */
+#include <acpi/codec_realtek.asl>
diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h b/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h
new file mode 100644
index 0000000000..f156004f9b
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/cyan/irqroute.h>
+
+/*
+ * Calculation of gpio based irq.
+ * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
+ * Max direct irq (MAX_DIRECT_IRQ) is 114.
+ * Size of gpio banks are
+ * GPSW_SIZE = 98
+ * GPNC_SIZE = 73
+ * GPEC_SIZE = 27
+ * GPSE_SIZE = 86
+ */
+
+/* KBD: Gpio index in N bank */
+#define BOARD_I8042_GPIO_INDEX		17
+/* Audio: Gpio index in SW bank */
+#define JACK_DETECT_GPIO_INDEX		95
+/* SCI: Gpio index in N bank */
+#define BOARD_SCI_GPIO_INDEX		15
+/* Trackpad: Gpio index in N bank */
+#define BOARD_TRACKPAD_GPIO_INDEX	18
+
+#define BOARD_TRACKPAD_NAME		"trackpad"
+#define BOARD_TRACKPAD_WAKE_GPIO	ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS		5
+#define BOARD_TRACKPAD_I2C_ADDR		0x4a
+
+/* SD CARD gpio */
+#define SDCARD_CD			81
+
+#define AUDIO_CODEC_HID			"10EC5650"
+#define AUDIO_CODEC_CID			"10EC5650"
+#define AUDIO_CODEC_DDN			"RTEK Codec Controller"
+#define AUDIO_CODEC_I2C_ADDR		0x1A
+
+#endif