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authorSridhar Siricilla <sridhar.siricilla@intel.com>2021-06-05 19:58:58 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-08 15:25:29 +0000
commitc07d2e5a9b8d9e5c9db183ae243b4a92dba67d95 (patch)
tree0f8aff87118c3e8509b5e6af95ad1c1bb781dbc0 /src/mainboard/google/cyan/com_init.c
parentc54968d977a219c5910108a44c9526c64aba2bc5 (diff)
soc/intel/alderlake: Correct TCSS XHCI Port status offset
The patch corrects TCSS XHCI Port status offset and CPU USB2 port count. The information is captured from the ADL-P Processor EDS Volume 2b of 2 (DOC ID:619503). BUG=None TEST=Verified boot on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/mainboard/google/cyan/com_init.c')
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