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| author | Tarun Tuli <taruntuli@google.com> | 2022-08-29 13:39:58 -0400 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-09-09 14:59:13 +0000 |
| commit | 2b523ce6316e5c5ec86fe812d739fe48ca81d83d (patch) | |
| tree | 933a7715f717fcd2eb092d3b4f43d8819fd18b3f /src/mainboard/google/brya/variants/vell | |
| parent | 0f08d37d20d3a859b4b12f5420b2554db98a1500 (diff) | |
mb/google/brya: Invoke power cycle of FPMCU on startup
Add functionality such that the FPMCU is power cycled and has its reset
sequenced on boot.
This has been added such that we do not need to update the bootblock.
We are required to do this as bootblock exists in read-only flash for
devices that have already been manufactured and so have no method of
updating the sequencing there.
Power remains off during coreboot (after briefly being turned on in the
unchangeable bootblock).
Once control is handed over to the Kernel, it takes care of sequencing
the power and reset appropriately and ensures the FPMCU is unpowered for
>200ms on boot.
BUG=b:240626388
TEST=Confirmed FPMCU is still functional on Vell and Anahera.
Confirmed power is off for approximately 6 seconds on boot (target
>200ms).
Confirmed reset is de-asserted approx 5ms after power application
(target >2.5ms)
Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/vell')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/gpio.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 4 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index cd889c780a..90e20a68db 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -175,6 +175,11 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_B4, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), + + /* D1 : ISH_GP1 ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 0, DEEP), }; const struct pad_config *variant_romstage_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 3d42f4be28..278c2406e5 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -416,6 +416,10 @@ chip soc/intel/alderlake register "compat_string" = ""google,cros-ec-spi"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" + register "enable_delay_ms" = "3" device spi 0 on end end # FPMCU end |