mb/google/brya: Invoke power cycle of FPMCU on startup

Add functionality such that the FPMCU is power cycled and has its reset
sequenced on boot.

This has been added such that we do not need to update the bootblock.
We are required to do this as bootblock exists in read-only flash for
devices that have already been manufactured and so have no method of
updating the sequencing there.

Power remains off during coreboot (after briefly being turned on in the
unchangeable bootblock).

Once control is handed over to the Kernel, it takes care of sequencing
the power and reset appropriately and ensures the FPMCU is unpowered for
>200ms on boot.

BUG=b:240626388
TEST=Confirmed FPMCU is still functional on Vell and Anahera.
Confirmed power is off for approximately 6 seconds on boot (target
>200ms).
Confirmed reset is de-asserted approx 5ms after power application
(target >2.5ms)

Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

39 files changed, 185 insertions, 2 deletions

diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c
index 02ebeb8ee3..09c1c26a7e 100644
--- a/src/mainboard/google/brya/variants/anahera/gpio.c
+++ b/src/mainboard/google/brya/variants/anahera/gpio.c
@@ -158,6 +158,12 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 7a46e95d55..df7f63248a 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -278,6 +278,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c
index 12f73fc014..aec61887a9 100644
--- a/src/mainboard/google/brya/variants/anahera4es/gpio.c
+++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c
@@ -158,6 +158,12 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
index 2b55270f2a..e2cf5b3200 100644
--- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
@@ -270,6 +270,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
index 8b62f3c4db..9e2be67707 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
@@ -120,9 +120,9 @@ static const struct pad_config gpio_table[] = {
 	/* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
 	PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
 	/* D1  : ISH_GP1 ==> FP_RST_ODL */
-	PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
+	PAD_CFG_GPO_LOCK(GPP_D1, 0, LOCK_CONFIG),
 	/* D2  : ISH_GP2 ==> EN_FP_PWR */
-	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
+	PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG),
 	/* D3  : ISH_GP3 ==> WCAM_RST_L */
 	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
 	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c
index c99115e524..1938d5ae1c 100644
--- a/src/mainboard/google/brya/variants/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/brask/gpio.c
@@ -65,6 +65,11 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index 03bdb533cf..88c73adce7 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -164,6 +164,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c
index 251348beaa..cab187a066 100644
--- a/src/mainboard/google/brya/variants/brya0/gpio.c
+++ b/src/mainboard/google/brya/variants/brya0/gpio.c
@@ -166,6 +166,12 @@ static const struct pad_config early_gpio_table_id4[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 1d00f94990..74884d4d01 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -703,6 +703,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/brya4es/gpio.c b/src/mainboard/google/brya/variants/brya4es/gpio.c
index 4cf99df49f..b343deafce 100644
--- a/src/mainboard/google/brya/variants/brya4es/gpio.c
+++ b/src/mainboard/google/brya/variants/brya4es/gpio.c
@@ -120,6 +120,12 @@ static const struct pad_config early_gpio_table_id2[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
index bcae9b3b9a..de10765ceb 100644
--- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
@@ -640,6 +640,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c
index 1102b0a03e..7e7fa3e527 100644
--- a/src/mainboard/google/brya/variants/crota/gpio.c
+++ b/src/mainboard/google/brya/variants/crota/gpio.c
@@ -196,6 +196,11 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_A19, 1, DEEP),
 	/* A20 : EXT_PWR_GATE2# ==> WWAN_RST_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_A20, 0, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb
index 2f9219e123..2843748bd3 100644
--- a/src/mainboard/google/brya/variants/crota/overridetree.cb
+++ b/src/mainboard/google/brya/variants/crota/overridetree.cb
@@ -271,6 +271,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c
index 12c2df561c..66555d7652 100644
--- a/src/mainboard/google/brya/variants/gimble/gpio.c
+++ b/src/mainboard/google/brya/variants/gimble/gpio.c
@@ -161,6 +161,11 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 	/* D18 : UART1_TXD ==> SD_PE_RST_L */
 	PAD_CFG_GPO(GPP_D18, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 2bd6ce5431..28519f6d34 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -236,6 +236,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/gimble4es/gpio.c b/src/mainboard/google/brya/variants/gimble4es/gpio.c
index a4ed7fb60b..84a56e1c42 100644
--- a/src/mainboard/google/brya/variants/gimble4es/gpio.c
+++ b/src/mainboard/google/brya/variants/gimble4es/gpio.c
@@ -161,6 +161,11 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 	/* D18 : UART1_TXD ==> SD_PE_RST_L */
 	PAD_CFG_GPO(GPP_D18, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
index dcfcae1144..4112cc39ad 100644
--- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
@@ -200,6 +200,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c
index 8ef3c39a0f..4dee174bbc 100644
--- a/src/mainboard/google/brya/variants/kano/gpio.c
+++ b/src/mainboard/google/brya/variants/kano/gpio.c
@@ -170,6 +170,11 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index ed646d0590..c28dd28b5a 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -407,6 +407,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c
index c224866dc8..b2ce931c76 100644
--- a/src/mainboard/google/brya/variants/primus/gpio.c
+++ b/src/mainboard/google/brya/variants/primus/gpio.c
@@ -138,8 +138,15 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 25085af74d..c91a2bb688 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -295,6 +295,10 @@ chip soc/intel/alderlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				device spi 0 on end
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 			end # FPMCU
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c
index 5947b6e2e1..8eaad78a18 100644
--- a/src/mainboard/google/brya/variants/primus4es/gpio.c
+++ b/src/mainboard/google/brya/variants/primus4es/gpio.c
@@ -138,8 +138,15 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
index c6bb44f25b..c55fa11d98 100644
--- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
@@ -284,6 +284,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c
index b82f4035cb..dfa68f9872 100644
--- a/src/mainboard/google/brya/variants/redrix/gpio.c
+++ b/src/mainboard/google/brya/variants/redrix/gpio.c
@@ -134,6 +134,12 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 8ee8710672..68e25c8c80 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -449,6 +449,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/redrix4es/gpio.c b/src/mainboard/google/brya/variants/redrix4es/gpio.c
index ee784723e6..5df642907b 100644
--- a/src/mainboard/google/brya/variants/redrix4es/gpio.c
+++ b/src/mainboard/google/brya/variants/redrix4es/gpio.c
@@ -131,6 +131,12 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index 1dc0e64dd2..c604d98d95 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -453,6 +453,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/skolas/gpio.c b/src/mainboard/google/brya/variants/skolas/gpio.c
index 251348beaa..cab187a066 100644
--- a/src/mainboard/google/brya/variants/skolas/gpio.c
+++ b/src/mainboard/google/brya/variants/skolas/gpio.c
@@ -166,6 +166,12 @@ static const struct pad_config early_gpio_table_id4[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index 9d2b0a2109..98db23d14d 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -703,6 +703,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/skolas4es/gpio.c b/src/mainboard/google/brya/variants/skolas4es/gpio.c
index 251348beaa..cab187a066 100644
--- a/src/mainboard/google/brya/variants/skolas4es/gpio.c
+++ b/src/mainboard/google/brya/variants/skolas4es/gpio.c
@@ -166,6 +166,12 @@ static const struct pad_config early_gpio_table_id4[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
index bf72f208e9..1a91779bf1 100644
--- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
@@ -731,6 +731,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c
index 2005760266..b552a602f3 100644
--- a/src/mainboard/google/brya/variants/taeko/gpio.c
+++ b/src/mainboard/google/brya/variants/taeko/gpio.c
@@ -204,6 +204,11 @@ static const struct pad_config romstage_gpio_table[] = {
 	 * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
 	 */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 7811b4be07..e358054fa5 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -555,6 +555,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c
index f87452a87d..4ab8a183c2 100644
--- a/src/mainboard/google/brya/variants/taeko4es/gpio.c
+++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c
@@ -204,6 +204,11 @@ static const struct pad_config romstage_gpio_table[] = {
 	 * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
 	 */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
index f598dbcfa6..5ab4afe560 100644
--- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
@@ -410,6 +410,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c
index cd889c780a..90e20a68db 100644
--- a/src/mainboard/google/brya/variants/vell/gpio.c
+++ b/src/mainboard/google/brya/variants/vell/gpio.c
@@ -175,6 +175,11 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 };
 
 const struct pad_config *variant_romstage_gpio_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 3d42f4be28..278c2406e5 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -416,6 +416,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end
diff --git a/src/mainboard/google/brya/variants/volmar/gpio.c b/src/mainboard/google/brya/variants/volmar/gpio.c
index 147e6c23f7..1ccb2b3ee0 100644
--- a/src/mainboard/google/brya/variants/volmar/gpio.c
+++ b/src/mainboard/google/brya/variants/volmar/gpio.c
@@ -179,6 +179,11 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config romstage_gpio_table[] = {
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb
index 3f1d115eb8..ce5cbdaf81 100644
--- a/src/mainboard/google/brya/variants/volmar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb
@@ -317,6 +317,10 @@ chip soc/intel/alderlake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
 				device spi 0 on end
 			end # FPMCU
 		end