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authorNick Vaccaro <nvaccaro@google.com>2023-11-17 10:33:07 -0800
committerFelix Held <felix-coreboot@felixheld.de>2023-11-20 14:33:39 +0000
commitf6113ececc56d748328243f94da08d1253df810d (patch)
treec2a3f08eee9a77fef6de46d09b4e47e8cee2c271 /src/mainboard/google/brya/variants/skolas/overridetree.cb
parentb57f87fb9ae514a2c0bf0825d8c410af48b05b3f (diff)
mb/goog/brya/var/skolas: sync slolas overridetree with brya0
Skolas uses brya0 schematic, so override tree should be almost the same for brya0 and skolas. This change sync's the skolas overridetree.cb with brya0's overridetree.cb. BUG=b:311722825 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/skolas/overridetree.cb')
-rw-r--r--src/mainboard/google/brya/variants/skolas/overridetree.cb87
1 files changed, 81 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index 388ea4f053..bb6d1eac08 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -132,7 +132,7 @@ chip soc/intel/alderlake
# TCP1 (DP-2) for port C1
register "device[3].name" = ""DD03""
register "device[3].use_pld" = "true"
- register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
@@ -548,7 +548,9 @@ chip soc/intel/alderlake
register "link_freq[1]" = "180 * MHz" # 180 MHz
register "remote_name" = ""IPU0""
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
register "has_power_resource" = "1"
+
#Controls
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
@@ -582,9 +584,23 @@ chip soc/intel/alderlake
register "chip_name" = ""DW9768 VCM""
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
- register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
register "vcm_compat" = ""dongwoon,dw9768""
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+ register "has_power_resource" = "1"
+
+ #Controls
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_WCAM_PWR
+
+ #_ON
+ register "on_seq.ops_cnt" = "1"
+ register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "1"
+ register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
device i2c 0C on
probe WFC WFC_MIPI_OVTI8856
end
@@ -595,7 +611,6 @@ chip soc/intel/alderlake
register "chip_name" = ""AT24 EEPROM""
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
- register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
register "nvm_compat" = ""atmel,24c1024""
register "nvm_size" = "0x2800"
@@ -603,6 +618,21 @@ chip soc/intel/alderlake
register "nvm_readonly" = "0x01"
register "nvm_width" = "0x10"
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+ register "has_power_resource" = "1"
+
+ #Controls
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_WCAM_PWR
+
+ #_ON
+ register "on_seq.ops_cnt" = "1"
+ register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "1"
+ register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
device i2c 58 on
probe WFC WFC_MIPI_OVTI8856
end
@@ -623,6 +653,8 @@ chip soc/intel/alderlake
register "link_freq[1]" = "180 * MHz" # 180 MHz
register "remote_name" = ""IPU0""
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
register "has_power_resource" = "1"
#Controls
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
@@ -657,9 +689,23 @@ chip soc/intel/alderlake
register "chip_name" = ""DW AF DAC""
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
- register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
register "vcm_compat" = ""dongwoon,dw9714""
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+ register "has_power_resource" = "1"
+
+ #Controls
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_WCAM_PWR
+
+ #_ON
+ register "on_seq.ops_cnt" = "1"
+ register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "1"
+ register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
device i2c 0C on
probe WFC WFC_MIPI_KBAE350
end
@@ -670,7 +716,6 @@ chip soc/intel/alderlake
register "chip_name" = ""GT24C08""
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
- register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
register "nvm_compat" = ""atmel,24c08""
register "nvm_size" = "0x2000"
@@ -678,6 +723,21 @@ chip soc/intel/alderlake
register "nvm_readonly" = "0x01"
register "nvm_width" = "0x10"
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+ register "has_power_resource" = "1"
+
+ #Controls
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_WCAM_PWR
+
+ #_ON
+ register "on_seq.ops_cnt" = "1"
+ register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "1"
+ register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
device i2c 50 on
probe WFC WFC_MIPI_KBAE350
end
@@ -800,6 +860,7 @@ chip soc/intel/alderlake
register "link_freq[0]" = "384 * MHz" # 384 MHz
register "link_freq[1]" = "96 * MHz" # 96 MHz
register "remote_name" = ""IPU0""
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
register "has_power_resource" = "1"
#Controls
@@ -834,7 +895,6 @@ chip soc/intel/alderlake
register "chip_name" = ""GT24C16S""
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
- register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC""
register "nvm_compat" = ""atmel,24c1024""
register "nvm_size" = "0x800"
@@ -842,6 +902,21 @@ chip soc/intel/alderlake
register "nvm_readonly" = "0x01"
register "nvm_width" = "0x08"
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+ register "has_power_resource" = "1"
+
+ #Controls
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_C3" #PP3300_FCAM_X
+
+ #_ON
+ register "on_seq.ops_cnt" = "1"
+ register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "1"
+ register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
device i2c 50 on
probe UFC UFC_MIPI_IMX208
end