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authorTarun Tuli <taruntuli@google.com>2022-08-29 13:39:58 -0400
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-09-09 14:59:13 +0000
commit2b523ce6316e5c5ec86fe812d739fe48ca81d83d (patch)
tree933a7715f717fcd2eb092d3b4f43d8819fd18b3f /src/mainboard/google/brya/variants/primus/overridetree.cb
parent0f08d37d20d3a859b4b12f5420b2554db98a1500 (diff)
mb/google/brya: Invoke power cycle of FPMCU on startup
Add functionality such that the FPMCU is power cycled and has its reset sequenced on boot. This has been added such that we do not need to update the bootblock. We are required to do this as bootblock exists in read-only flash for devices that have already been manufactured and so have no method of updating the sequencing there. Power remains off during coreboot (after briefly being turned on in the unchangeable bootblock). Once control is handed over to the Kernel, it takes care of sequencing the power and reset appropriately and ensures the FPMCU is unpowered for >200ms on boot. BUG=b:240626388 TEST=Confirmed FPMCU is still functional on Vell and Anahera. Confirmed power is off for approximately 6 seconds on boot (target >200ms). Confirmed reset is de-asserted approx 5ms after power application (target >2.5ms) Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/primus/overridetree.cb')
-rw-r--r--src/mainboard/google/brya/variants/primus/overridetree.cb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 25085af74d..c91a2bb688 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -295,6 +295,10 @@ chip soc/intel/alderlake
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
register "wake" = "GPE0_DW2_15"
device spi 0 on end
+ register "has_power_resource" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+ register "enable_delay_ms" = "3"
end # FPMCU
end
device ref pch_espi on