diff options
| author | Zhuohao Lee <zhuohao@chromium.org> | 2021-12-29 15:17:41 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-07 03:07:07 +0000 |
| commit | e2192e6a82e37cb40216c98dfd0183dc146eac37 (patch) | |
| tree | 98e678bba2655092bc53e7532880fdd37713f7ac /src/mainboard/google/brya/variants/brask | |
| parent | f58ce3bdaaf5a7fb0047433b2d7ce18690a65058 (diff) | |
mb/google/brya/var/brask: Change TPM I2C to I2C1
The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch
moves the TPM I2C setting from the board layer to the baseboard and
fixes the TPM I2C bus assignment.
BUG=b:211886429
TEST=build pass
Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60439
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/brask')
| -rw-r--r-- | src/mainboard/google/brya/variants/brask/gpio.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/brask/overridetree.cb | 7 |
2 files changed, 4 insertions, 11 deletions
diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c index 86a906e0c2..c99115e524 100644 --- a/src/mainboard/google/brya/variants/brask/gpio.c +++ b/src/mainboard/google/brya/variants/brask/gpio.c @@ -11,10 +11,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -32,6 +28,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 9a0e073c98..b7e9fef7ae 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -153,13 +153,6 @@ chip soc/intel/alderlake device i2c 1a on end end end - device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" |