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-rw-r--r--src/mainboard/google/brya/Kconfig2
-rw-r--r--src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb15
-rw-r--r--src/mainboard/google/brya/variants/baseboard/brask/gpio.c24
-rw-r--r--src/mainboard/google/brya/variants/brask/gpio.c8
-rw-r--r--src/mainboard/google/brya/variants/brask/overridetree.cb7
5 files changed, 29 insertions, 27 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 06ba53113e..9d80ec3c22 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -87,7 +87,7 @@ config DRIVER_TPM_I2C_BUS
hex
default 0x3 if BOARD_GOOGLE_BRYA0
default 0x3 if BOARD_GOOGLE_BRYA4ES
- default 0x3 if BOARD_GOOGLE_BRASK
+ default 0x1 if BOARD_GOOGLE_BRASK
default 0x1 if BOARD_GOOGLE_PRIMUS
default 0x3 if BOARD_GOOGLE_PRIMUS4ES
default 0x1 if BOARD_GOOGLE_GIMBLE
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index 4662b9586d..d9a4e42c04 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -77,7 +77,7 @@ chip soc/intel/alderlake
#+-------------------+---------------------------+
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio |
- #| I2C3 | cr50 TPM. Early init is |
+ #| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#+-------------------+---------------------------+
@@ -85,9 +85,12 @@ chip soc/intel/alderlake
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
- .i2c[3] = {
+ .i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
+ .rise_time_ns = 600,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
},
}"
@@ -108,7 +111,13 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
- device ref i2c3 on end
+ device ref i2c1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+ device i2c 50 on end
+ end
+ end
device ref heci1 on end
device ref sata on end
device ref pcie_rp7 on
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
index 42c0275875..268cddc999 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
@@ -65,10 +65,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
/* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
- /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
- PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
- /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
- PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+ /* B7 : ISH_12C1_SDA ==> NC */
+ PAD_NC(GPP_B7, NONE),
+ /* B8 : ISH_I2C1_SCL ==> NC */
+ PAD_NC(GPP_B8, NONE),
/* B9 : NC */
PAD_NC(GPP_B9, NONE),
/* B10 : NC */
@@ -268,10 +268,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
- /* H6 : I2C1_SDA ==> NC */
- PAD_NC(GPP_H6, NONE),
- /* H7 : I2C1_SCL ==> NC */
- PAD_NC(GPP_H7, NONE),
+ /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
/* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */
@@ -371,10 +371,6 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
- /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
- PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
- /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
- PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
/*
* D1 : ISH_GP1 ==> FP_RST_ODL
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
@@ -390,6 +386,10 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F14 : GSXDIN ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_F14, 1, DEEP),
+ /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c
index 86a906e0c2..c99115e524 100644
--- a/src/mainboard/google/brya/variants/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/brask/gpio.c
@@ -11,10 +11,6 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
- /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
- PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
- /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
- PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
/*
* D1 : ISH_GP1 ==> FP_RST_ODL
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
@@ -32,6 +28,10 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_F14, 1, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+ /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index 9a0e073c98..b7e9fef7ae 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -153,13 +153,6 @@ chip soc/intel/alderlake
device i2c 1a on end
end
end
- device ref i2c3 on
- chip drivers/i2c/tpm
- register "hid" = ""GOOG0005""
- register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
- device i2c 50 on end
- end
- end
device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"