mb/google/brya: Add new baseboard nissa with variants nivviks and nereid

Add a new baseboard for nissa, an Intel ADL-N based reference design.
Also, add variants for the two reference boards, nivviks and nereid.
This commit is a stub which only adds the minimum code needed for a
successful build.

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
     abuild -a -x -c max -p none -t google/brya -b nereid

Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

6 files changed, 116 insertions, 0 deletions

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc
new file mode 100644
index 0000000000..1693d2e263
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc
@@ -0,0 +1,6 @@
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
new file mode 100644
index 0000000000..a5e2217fef
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -0,0 +1,4 @@
+chip soc/intel/alderlake
+	device domain 0 on
+	end
+end
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
new file mode 100644
index 0000000000..9471031014
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <types.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* TODO */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* TODO */
+};
+
+const struct pad_config *__weak variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *__weak variant_gpio_override_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	/* TODO */
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
+
+const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h
new file mode 100644
index 0000000000..a2210c63fa
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+/* TODO: Set the correct values */
+#define MAINBOARD_EC_SCI_EVENTS		0
+#define MAINBOARD_EC_SMI_EVENTS		0
+#define MAINBOARD_EC_S5_WAKE_EVENTS	0
+#define MAINBOARD_EC_S3_WAKE_EVENTS	0
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	0
+#define MAINBOARD_EC_LOG_EVENTS		0
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
new file mode 100644
index 0000000000..9ca9ee7452
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* TODO: Set the correct values */
+#define EC_SCI_GPI		0
+#define GPIO_PCH_WP		0
+#define GPIO_EC_IN_RW		0
+#define GPIO_SLP_S0_GATE	0
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/memory.c b/src/mainboard/google/brya/variants/baseboard/nissa/memory.c
new file mode 100644
index 0000000000..420b36697b
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/memory.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	/* TODO */
+	return NULL;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	/* TODO */
+	return false;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	/* TODO */
+}