aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/google/auron/variants/lulu/overridetree.cb
diff options
context:
space:
mode:
authorMatt DeVillier <matt.devillier@gmail.com>2020-03-30 13:21:45 -0500
committerMatt DeVillier <matt.devillier@gmail.com>2020-04-03 16:21:55 +0000
commitae01122b57eed272d6a10013b4686826dbfb95be (patch)
tree46b35a3b2ae69e6deade1c3bd6b51f5ce4f78a49 /src/mainboard/google/auron/variants/lulu/overridetree.cb
parentb54c5168bd1e82deee9f2bb0019490c167a66daf (diff)
mb/google/auron: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. As part of the cleanup, drop unused PCIe RP5 for buddy as well. Test: build all auron variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will) Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/auron/variants/lulu/overridetree.cb')
-rw-r--r--src/mainboard/google/auron/variants/lulu/overridetree.cb16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
new file mode 100644
index 0000000000..70b1ebd552
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -0,0 +1,16 @@
+chip soc/intel/broadwell
+
+ # Enable Panel and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "5" # 400ms
+ register "gpu_panel_power_up_delay" = "400" # 40ms
+ register "gpu_panel_power_down_delay" = "150" # 15ms
+ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
+
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
+
+ device domain 0 on end
+end