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authorThaminda Edirisooriya <thaminda@google.com>2015-07-29 17:43:20 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-08-09 19:56:52 +0200
commit8fad21db54d1435333f832767fb65312db103eb2 (patch)
tree108112f06e092b01695d7f045aec981a7c3be32a /src/mainboard/emulation/spike-riscv/devicetree.cb
parentd7eb0cbf9ad27d667d68dae449226b5b789f3db2 (diff)
riscv-spike: support for Spike emulation of riscv
Spike support: QEMU RISCV is broken, and the maintainers at Berkeley are working on it, but at the moment spike is the only way to test on riscv. Add support for spike console output for debugging. Privileged ISA: Update to privileged ISA in RISCV (machine, supervisor, hypervisor, user modes) broke exisitng RISCV asm, and bootblock.S was updated to match the new spec. Clean old assembly [pg: things build with gcc 4.9 now, but don't expect them to work. Hardcoding register names into the assembler language may not be the smartest idea of the RISCV folks.] Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv/devicetree.cb')
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1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/emulation/spike-riscv/devicetree.cb b/src/mainboard/emulation/spike-riscv/devicetree.cb
new file mode 100644
index 0000000000..e3ce08829e
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+chip soc/ucb/riscv
+ device cpu_cluster 0 on end
+ chip drivers/generic/generic # I2C0 controller
+ device i2c 6 on end # Fake component for testing
+ end
+end