riscv-spike: support for Spike emulation of riscv

Spike support: QEMU RISCV is broken, and the maintainers at Berkeley
are working on it, but at the moment spike is the only way to  test
on riscv. Add support for spike console output for debugging.

Privileged ISA: Update to privileged ISA in RISCV (machine,
supervisor, hypervisor, user modes) broke exisitng RISCV asm, and
bootblock.S was updated to match the new spec. Clean old assembly

[pg: things build with gcc 4.9 now, but don't expect them to work.
Hardcoding register names into the assembler language may not be the smartest
idea of the RISCV folks.]

Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

11 files changed, 377 insertions, 0 deletions

diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig
new file mode 100644
index 0000000000..7c7fb346a4
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/Kconfig
@@ -0,0 +1,61 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+
+# To execute, do:
+# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
+
+if BOARD_EMULATION_SPIKE_UCB_RISCV
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SOC_UCB_RISCV
+	select BOARD_ROMSIZE_KB_4096
+	select ARCH_BOOTBLOCK_RISCV
+	select HAVE_UART_SPECIAL
+
+config MAINBOARD_DIR
+	string
+	default emulation/spike-riscv
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "SPIKE RISCV"
+
+config MAX_CPUS
+	int
+	default 1
+
+config MAINBOARD_VENDOR
+	string
+	default "UCB"
+
+config DRAM_SIZE_MB
+	int
+	default 32768
+
+# Memory map for qemu riscv
+#
+# 0x0000_0000: jump instruction (by qemu)
+# 0x0002_0000: bootblock (entry of kernel / firmware)
+# 0x0003_0000: romstage, assume up to 128KB in size.
+# 0x0007_ff00: stack pointer
+# 0x0010_0000: CBFS header
+# 0x0011_0000: CBFS data
+# 0x0100_0000: reserved for ramstage
+
+config RAMTOP
+	hex
+	default 0x1000000
+
+endif #  BOARD_EMULATION_SPIKE_UCB_RISCV
diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name
new file mode 100644
index 0000000000..36dd509eb0
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_EMULATION_SPIKE_UCB_RISCV
+	bool "SPIKE ucb riscv"
diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc
new file mode 100644
index 0000000000..dff4758173
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/Makefile.inc
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+
+bootblock-y += bootblock.c
+bootblock-y += uart.c
+bootblock-y += spike_util.c
+romstage-y += romstage.c
+romstage-y += uart.c
+romstage-y += spike_util.c
+ramstage-y += uart.c
+ramstage-y += spike_util.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/spike-riscv/board_info.txt b/src/mainboard/emulation/spike-riscv/board_info.txt
new file mode 100644
index 0000000000..811e8e0840
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/board_info.txt
@@ -0,0 +1,2 @@
+Board name: QEMU RISCV
+Category: emulation
diff --git a/src/mainboard/emulation/spike-riscv/bootblock.c b/src/mainboard/emulation/spike-riscv/bootblock.c
new file mode 100644
index 0000000000..56f2eca863
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/bootblock.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/exception.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <program_loading.h>
+
+// the qemu part of all this is very, very non-hardware like.
+// so it gets its own bootblock.
+void main(void)
+{
+	if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+		console_init();
+		exception_init();
+	}
+	run_romstage();
+}
diff --git a/src/mainboard/emulation/spike-riscv/devicetree.cb b/src/mainboard/emulation/spike-riscv/devicetree.cb
new file mode 100644
index 0000000000..e3ce08829e
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+
+chip soc/ucb/riscv
+	device cpu_cluster 0 on end
+	chip drivers/generic/generic # I2C0 controller
+		device i2c 6 on end # Fake component for testing
+	end
+end
diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv/mainboard.c
new file mode 100644
index 0000000000..111e9b185b
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/mainboard.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <cbmem.h>
+
+static void mainboard_enable(device_t dev)
+{
+
+	if (!dev) {
+		printk(BIOS_EMERG, "No dev0; die\n");
+		while (1);
+	}
+
+	ram_resource(dev, 0, 2048, 32768);
+	cbmem_recovery(0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
new file mode 100644
index 0000000000..8801f3520b
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+SECTIONS
+{
+	DRAM_START(0x0)
+	BOOTBLOCK(0x0, 64K)
+	ROMSTAGE(0x20000, 128K)
+	STACK(0x40000, 0x3ff00)
+	PRERAM_CBMEM_CONSOLE(0x80000, 8K)
+	RAMSTAGE(0x100000, 16M)
+}
diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv/romstage.c
new file mode 100644
index 0000000000..b6314ccd1c
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/romstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <program_loading.h>
+
+void main(void)
+{
+	console_init();
+	run_ramstage();
+}
diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c
new file mode 100644
index 0000000000..b34ff4a0d0
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/spike_util.c
@@ -0,0 +1,82 @@
+#include <spike_util.h>
+
+uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) {
+        uintptr_t fromhost = swap_csr(mfromhost, 0);
+        if (!fromhost)
+        return 0;
+
+        uintptr_t dev = FROMHOST_DEV(fromhost);
+        uintptr_t cmd = FROMHOST_CMD(fromhost);
+        uintptr_t data = FROMHOST_DATA(fromhost);
+
+        sbi_device_message* m = HLS()->device_request_queue_head;
+        sbi_device_message* prev = 0x0;
+        unsigned long i, n;
+        for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) {
+                /*
+                if (!supervisor_paddr_valid(m, sizeof(*m))
+                && EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M)
+                panic("htif: page fault");
+                */
+
+                sbi_device_message* next = (void*)m->sbi_private_data;
+                if (m->dev == dev && m->cmd == cmd) {
+                        m->data = data;
+
+                        // dequeue from request queue
+                        if (prev)
+                        prev->sbi_private_data = (uintptr_t)next;
+                        else
+                        HLS()->device_request_queue_head = next;
+                        HLS()->device_request_queue_size = n-1;
+                        m->sbi_private_data = 0;
+
+                        // enqueue to response queue
+                        if (HLS()->device_response_queue_tail)
+                        {
+                                HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m;
+                        }
+                        else
+                        {
+                                HLS()->device_response_queue_head = m;
+                        }
+                        HLS()->device_response_queue_tail = m;
+
+                        // signal software interrupt
+                        set_csr(mip, MIP_SSIP);
+                        return 0;
+                }
+
+                prev = m;
+                m = (void*)atomic_read(&m->sbi_private_data);
+        }
+        //HLT();
+        return 0;
+        //panic("htif: no record");
+}
+
+uintptr_t mcall_console_putchar(uint8_t ch)
+{
+        while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0);
+        while (1) {
+                uintptr_t fromhost = read_csr(mfromhost);
+                if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) {
+                if (fromhost)
+                htif_interrupt(0, 0);
+                continue;
+        }
+        write_csr(mfromhost, 0);
+        break;
+        }
+        return 0;
+}
+
+void testPrint(void) {
+        /* Print a test command to check Spike console output */
+        mcall_console_putchar('h');
+        mcall_console_putchar('e');
+        mcall_console_putchar('l');
+        mcall_console_putchar('l');
+        mcall_console_putchar('o');
+        mcall_console_putchar('\n');
+}
diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c
new file mode 100644
index 0000000000..961ddc56d4
--- /dev/null
+++ b/src/mainboard/emulation/spike-riscv/uart.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <types.h>
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <spike_util.h>
+
+static uint8_t *buf = (void *)0x3f8;
+uintptr_t uart_platform_base(int idx)
+{
+	return (uintptr_t) buf;
+}
+
+void uart_init(int idx)
+{
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+	return *buf; // this does not work on spike, requires more implementation details
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+	mcall_console_putchar(data);
+}
+
+void uart_tx_flush(int idx)
+{
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+	struct lb_serial serial;
+	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+	serial.baseaddr = 0x3f8;
+	serial.baud = 115200;
+	serial.regwidth = 1;
+	lb_add_serial(&serial, data);
+        lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif