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authorArthur Heymans <arthur@aheymans.xyz>2023-06-20 12:08:33 +0200
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2023-06-22 21:04:31 +0000
commite3929efd1e328280e36c4b14a4a1b7e26b259836 (patch)
treed0650ce00fc296968ee4a7591e6bdbbfeab9d6ea /src/mainboard/emulation/qemu-aarch64/mainboard.c
parent58fe703e088be0af934cc0bf31fc60f87fcfde76 (diff)
mb/qemu/aarch64: Add PCI support
Run with "-device pci-bridge,chassis_nr=1" argument to add a bridge and see that it gets found and picked up by the resource allocator. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iad5d87731066a4009d2c4930a01bc15543d9447a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75925 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/qemu-aarch64/mainboard.c')
-rw-r--r--src/mainboard/emulation/qemu-aarch64/mainboard.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c
index 181536ce03..09b983f330 100644
--- a/src/mainboard/emulation/qemu-aarch64/mainboard.c
+++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c
@@ -4,6 +4,7 @@
#include <symbols.h>
#include <device/device.h>
#include <bootmem.h>
+#include <mainboard/addressmap.h>
void bootmem_platform_add_ranges(void)
{
@@ -21,3 +22,32 @@ struct chip_operations mainboard_ops = {
};
struct chip_operations mainboard_emulation_qemu_aarch64_ops = { };
+
+static void qemu_aarch64_domain_read_resources(struct device *dev)
+{
+ struct resource *res;
+ int index = 0;
+ /* Initialize the system-wide I/O space constraints. */
+ res = new_resource(dev, index++);
+ res->limit = 0xffff;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
+
+ /* Initialize the system-wide memory resources constraints. */
+ res = new_resource(dev, index++);
+ res->base = VIRT_PCIE_LOW_MMIO_BASE;
+ res->limit = VIRT_PCIE_LOW_MMIO_LIMIT;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+ res = new_resource(dev, index++);
+ res->base = VIRT_PCIE_HIGH_MMIO_BASE;
+ res->limit = VIRT_PCIE_HIGH_MMIO_LIMIT;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+ mmio_range(dev, index++, VIRT_PCIE_ECAM_BASE, VIRT_PCIE_ECAM_SIZE);
+}
+
+struct device_operations qemu_aarch64_pci_domain_ops = {
+ .read_resources = qemu_aarch64_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+};