mb/qemu/aarch64: Add PCI support

Run with "-device pci-bridge,chassis_nr=1" argument to add a bridge and
see that it gets found and picked up by the resource allocator.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iad5d87731066a4009d2c4930a01bc15543d9447a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75925
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 61 insertions, 0 deletions

diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig
index 64d7d789dc..940b89dc61 100644
--- a/src/mainboard/emulation/qemu-aarch64/Kconfig
+++ b/src/mainboard/emulation/qemu-aarch64/Kconfig
@@ -21,6 +21,13 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MISSING_BOARD_RESET
 	select ARM64_USE_ARM_TRUSTED_FIRMWARE
+	select PCI
+
+config ECAM_MMCONF_BASE_ADDRESS
+	default 0x4010000000
+
+config ECAM_MMCONF_BUS_NUMBER
+	default 256
 
 config MEMLAYOUT_LD_FILE
 	string
diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock.c b/src/mainboard/emulation/qemu-aarch64/bootblock.c
index 45a9de455e..5fe0888e59 100644
--- a/src/mainboard/emulation/qemu-aarch64/bootblock.c
+++ b/src/mainboard/emulation/qemu-aarch64/bootblock.c
@@ -20,5 +20,8 @@ void bootblock_mainboard_init(void)
 
 	mmu_config_range(_bl31, REGION_SIZE(bl31), MA_MEM | MA_S | MA_RW);
 
+	mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
+			 MA_DEV | MA_RW);
+
 	mmu_enable();
 }
diff --git a/src/mainboard/emulation/qemu-aarch64/devicetree.cb b/src/mainboard/emulation/qemu-aarch64/devicetree.cb
index d887837a52..d6c76e1d46 100644
--- a/src/mainboard/emulation/qemu-aarch64/devicetree.cb
+++ b/src/mainboard/emulation/qemu-aarch64/devicetree.cb
@@ -2,4 +2,8 @@
 
 chip mainboard/emulation/qemu-aarch64
 	device cpu_cluster 0 on end
+
+	device domain 0 on ops qemu_aarch64_pci_domain_ops
+		device pci 00.0 on end
+	end
 end
diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
index 50dd35ebdc..70acac8519 100644
--- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
@@ -28,3 +28,20 @@
 #define VIRT_MMIO_BASE 0x0a000000
 #define VIRT_PLATFORM_BUS_BASE 0x0c000000
 #define VIRT_SECRAM_BASE 0xe000000
+#define VIRT_PCIE_LOW_MMIO_BASE 0x10000000
+#define VIRT_PCIE_LOW_MMIO_LIMIT 0x3efeffff
+/*
+ * From hw/arm/virt.c:
+ * Highmem IO Regions: This memory map is floating, located after the RAM.
+ * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
+ * top of the RAM, so that its base get the same alignment as the size,
+ * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
+ * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
+ * Note the extended_memmap is sized so that it eventually also includes the
+ * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
+ * index of base_memmap).
+ */
+#define VIRT_PCIE_ECAM_BASE 0x4010000000 /* The one in lower memory does not seem to work */
+#define VIRT_PCIE_ECAM_SIZE (256 * MiB)
+#define VIRT_PCIE_HIGH_MMIO_BASE 0x8000000000ULL
+#define VIRT_PCIE_HIGH_MMIO_LIMIT 0xffffffffffULL
diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c
index 181536ce03..09b983f330 100644
--- a/src/mainboard/emulation/qemu-aarch64/mainboard.c
+++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c
@@ -4,6 +4,7 @@
 #include <symbols.h>
 #include <device/device.h>
 #include <bootmem.h>
+#include <mainboard/addressmap.h>
 
 void bootmem_platform_add_ranges(void)
 {
@@ -21,3 +22,32 @@ struct chip_operations mainboard_ops = {
 };
 
 struct chip_operations mainboard_emulation_qemu_aarch64_ops = { };
+
+static void qemu_aarch64_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+	int index = 0;
+	/* Initialize the system-wide I/O space constraints. */
+	res = new_resource(dev, index++);
+	res->limit = 0xffff;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
+
+	/* Initialize the system-wide memory resources constraints. */
+	res = new_resource(dev, index++);
+	res->base = VIRT_PCIE_LOW_MMIO_BASE;
+	res->limit = VIRT_PCIE_LOW_MMIO_LIMIT;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+	res = new_resource(dev, index++);
+	res->base = VIRT_PCIE_HIGH_MMIO_BASE;
+	res->limit = VIRT_PCIE_HIGH_MMIO_LIMIT;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+	mmio_range(dev, index++, VIRT_PCIE_ECAM_BASE, VIRT_PCIE_ECAM_SIZE);
+}
+
+struct device_operations qemu_aarch64_pci_domain_ops = {
+	.read_resources    = qemu_aarch64_domain_read_resources,
+	.set_resources     = pci_domain_set_resources,
+	.scan_bus          = pci_domain_scan_bus,
+};