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authorMichał Żygowski <michal.zygowski@3mdeb.com>2024-07-04 17:19:38 +0200
committerFelix Held <felix-coreboot@felixheld.de>2024-07-22 13:59:32 +0000
commit203b9fb352f89c112325286cc651596da906a848 (patch)
tree12c71c4f20e6ff6438d0dd12480bd5668b20a04f /src/mainboard/clevo/Kconfig.name
parent8b17b9b1967c5299c021cb65e9322668ad32b9cc (diff)
soc/intel/alderlake/tcss: Add definition of IOM_READY bit
Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1 register. Needed by Protectli VP66XX boards to poll for this bit for about 2 seconds before FSP Silicon Init to have USB functionality. ME is supposed to start fetching and executing the TCSS IPs FW right after DRAM Init Done message, which happens after MRC. For most platforms the time interval between the end of MemoryInit and start of SiliconInit is enough for IOM_READY to get set. TEST=Poll the IOM_READY bit on VP66XX platform and observe the TCSS XHCI is up in lspci. Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83356 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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