diff options
| author | Keith Hui <buurin@gmail.com> | 2024-02-05 16:44:38 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-08 00:08:33 +0000 |
| commit | 51a57eb5ea782c3287719c8c7646ea726b14c78d (patch) | |
| tree | 7ff3a6b1424750e66d4349f41eeb7fcc7b10ab77 /src/mainboard/asus/p8x7x-series | |
| parent | 1acb3e118bf0bdba8f13f62304425f8c21dad2c8 (diff) | |
mb/*: Add consolidated USB port config for SNB+MRC boards
For each sandybridge boards with option to use MRC or native platform
init code, add a copy of the board's USB port config, consolidated between
both code paths, into the southbridge devicetree, using special values
allocated for this consolidation.
These get hooked up in a separate patch.
Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p8x7x-series')
| -rw-r--r-- | src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index da34af3b12..2cb94213e3 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -12,6 +12,22 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x000c0291" register "gen4_dec" = "0x0000ff29" register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {1, 2, 0}, + {1, 2, 0}, + {1, 2, 1}, + {1, 2, 1}, + {1, 2, 2}, + {1, 2, 2}, + {1, 2, 3}, + {1, 2, 3}, + {1, 2, 4}, + {1, 2, 4}, + {1, 2, 6}, + {1, 2, 5}, + {0, 2, 5}, + {0, 2, 6} + }" device ref pcie_rp1 on end # PCIEX_16_3 device ref pcie_rp2 on end # RTL8111F |