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| author | Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> | 2013-05-09 16:14:59 +0200 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-06-04 21:34:52 +0200 |
| commit | 649f18f834aaf13674e4c8e9a192b386165b39f1 (patch) | |
| tree | 83b7cfed7085fdcd60db3301a64bf749c14aafff /src/mainboard/asus/m4a785t-m/Kconfig | |
| parent | 03c66202dee7691c7ef7978a1d1fe555f1717834 (diff) | |
Asus M4A785T-M: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
and booting coreboot we have:
# ./nvramtool -a
boot_option = Fallback
last_boot = Fallback
ECC_memory = Enable
baud_rate = 115200
hw_scrubber = Enable
interleave_chip_selects = Enable
max_mem_clock = 400Mhz
multi_core = Enable
power_on_after_fail = Disable
debug_level = Spew
boot_first = HDD
boot_second = Fallback_Floppy
boot_third = Fallback_Network
boot_index = 0xf
boot_countdown = 0xc
slow_cpu = off
nmi = Enable
iommu = Enable
nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.
nvramtool: Warning: Coreboot CMOS checksum is bad.
Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3324
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/asus/m4a785t-m/Kconfig')
| -rw-r--r-- | src/mainboard/asus/m4a785t-m/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 10f6838ea7..6816d58ce0 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY |