diff options
| author | Keith Hui <buurin@gmail.com> | 2023-07-22 12:49:05 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 20:31:23 +0000 |
| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (patch) | |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 /src/mainboard/asus/h61-series/variants | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 (diff) | |
mb/*: Update SPD mapping for sandybridge boards
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/asus/h61-series/variants')
6 files changed, 1 insertions, 36 deletions
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c index cb8daaf014..50e225a0d4 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> @@ -35,9 +34,3 @@ void bootblock_mainboard_early_init(void) pnp_write_config(ACPI_DEV, 0xe4, 0x10); nuvoton_pnp_exit_conf_state(SIO_DEV); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c index 5e54d08e85..5f5c684aa2 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <device/dram/ddr3.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -30,9 +28,3 @@ void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c index 33efaf6e04..404a8503bf 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> @@ -47,9 +46,3 @@ void bootblock_mainboard_early_init(void) /* Do not enable UART, the header is not populated by default */ } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c index 05e87c1c68..1c8d84442b 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -49,9 +48,3 @@ void bootblock_mainboard_early_init(void) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c index af90702cfe..e76e1094cb 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -49,9 +48,3 @@ void bootblock_mainboard_early_init(void) /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x51, id_only); - read_spd(&spd[2], 0x53, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb index 7882bf0748..1b78b9b9bd 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x51, 0, 0x53, 0}" device domain 0 on chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" # HWM |