mb/*/*: Remove AMD FAMILY15TN boards

These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

24 files changed, 0 insertions, 1652 deletions

diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
deleted file mode 100644
index a426f01bfa..0000000000
--- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <northbridge/amd/agesa/state_machine.h>
-
-#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD,                 agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/**
- * ASUS F2A85-M board ALC887-VD Verb Table
- *
- * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
- * the vendor BIOS.
- */
-#if !CONFIG(BOARD_ASUS_F2A85_M_LE)
-const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
-	{0x11, 0x99430140},
-	{0x12, 0x411111f0},
-	{0x14, 0x01014010},
-	{0x15, 0x01011012},
-	{0x16, 0x01016011},
-	{0x17, 0x01012014},
-	{0x18, 0x01a19850},
-	{0x19, 0x02a19c60},
-	{0x1a, 0x0181305f},
-	{0x1b, 0x02214c20},
-	{0x1c, 0x411111f0},
-	{0x1d, 0x4005e601},
-	{0x1e, 0x01456130},
-	{0x1f, 0x411111f0},
-	{0xff, 0xffffffff}
-};
-#else
-const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
-	{0x11, 0x99430140},
-	{0x12, 0x411111f0},
-	{0x14, 0x01014010},
-	{0x15, 0x411111f0},
-	{0x16, 0x411111f0},
-	{0x17, 0x411111f0},
-	{0x18, 0x01a19850},
-	{0x19, 0x02a19c60},
-	{0x1a, 0x0181305f},
-	{0x1b, 0x02214c20},
-	{0x1c, 0x411111f0},
-	{0x1d, 0x4004c601},
-	{0x1e, 0x01456130},
-	{0x1f, 0x411111f0},
-	{0xff, 0xffffffff}
-};
-#endif
-
-static const CODEC_TBL_LIST CodecTableList[] =
-{
-	{0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]},
-	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
-};
-
-void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
-{
-	FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
-}
-
-void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
-{
-	/* Azalia Controller OEM Codec Table Pointer */
-	FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
-
-	/* Fan Control */
-	FchParams_env->Imc.ImcEnable = FALSE;
-	FchParams_env->Hwm.HwMonitorEnable = FALSE;
-	FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
-}
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
deleted file mode 100644
index a2e4f60341..0000000000
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ /dev/null
@@ -1,105 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY15_TN
-	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
-	select SOUTHBRIDGE_AMD_AGESA_HUDSON
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE
-	select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO
-	select SUPERIO_NUVOTON_COMMON_COM_A if BOARD_ASUS_F2A85_M_PRO
-	select BOARD_ROMSIZE_KB_8192
-	select GFXUMA
-
-choice
-	prompt "DDR3 memory voltage"
-	default BOARD_ASUS_F2A85_M_DDR3_VOLT_150
-
-config BOARD_ASUS_F2A85_M_DDR3_VOLT_135
-	bool "1.35V"
-	help
-	  Set DRR3 memory voltage to 1.35V
-config BOARD_ASUS_F2A85_M_DDR3_VOLT_150
-	bool "1.50V"
-	help
-	  Set DRR3 memory voltage to 1.50V
-config BOARD_ASUS_F2A85_M_DDR3_VOLT_165
-	bool "1.65V"
-	help
-	  Set DRR3 memory voltage to 1.65V
-endchoice
-
-config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL
-	hex
-	default 0x9e if BOARD_ASUS_F2A85_M_DDR3_VOLT_135
-	default 0x0 if BOARD_ASUS_F2A85_M_DDR3_VOLT_150
-	default 0x1e if BOARD_ASUS_F2A85_M_DDR3_VOLT_165
-
-config MAINBOARD_DIR
-	default "asus/f2a85-m"
-
-config MAINBOARD_PART_NUMBER
-	default "F2A85-M" if BOARD_ASUS_F2A85_M
-	default "F2A85-M_LE" if BOARD_ASUS_F2A85_M_LE
-	default "F2A85-M_PRO" if BOARD_ASUS_F2A85_M_PRO
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 4
-
-config HUDSON_XHCI_FWM
-	bool
-	default n
-
-config HUDSON_IMC_FWM
-	bool
-	default n
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
-
-config VGA_BIOS_ID
-	string
-	default "1002,9993"
-
-config HUDSON_LEGACY_FREE
-	bool
-	default n
-
-config POST_IO
-	bool
-	default n
-
-endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
-
-if BOARD_ASUS_F2A85_M_LE
-
-config VGA_BIOS_ID
-	string
-	default "1002,9901"
-
-endif
-
-config DEVICETREE
-	default "devicetree_f2a85-m_pro.cb" if BOARD_ASUS_F2A85_M_PRO
-	default "devicetree_f2a85-m.cb" if BOARD_ASUS_F2A85_M
-	default "devicetree_f2a85-m_le.cb" if BOARD_ASUS_F2A85_M_LE
-
-endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE
diff --git a/src/mainboard/asus/f2a85-m/Kconfig.name b/src/mainboard/asus/f2a85-m/Kconfig.name
deleted file mode 100644
index 8a3d7ef1d1..0000000000
--- a/src/mainboard/asus/f2a85-m/Kconfig.name
+++ /dev/null
@@ -1,8 +0,0 @@
-config BOARD_ASUS_F2A85_M
-	bool "F2A85-M"
-
-config BOARD_ASUS_F2A85_M_PRO
-	bool "F2A85-M PRO"
-
-config BOARD_ASUS_F2A85_M_LE
-	bool "F2A85-M LE"
diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc
deleted file mode 100644
index 549801d78f..0000000000
--- a/src/mainboard/asus/f2a85-m/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
deleted file mode 100644
index 930f1fcca2..0000000000
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <Porting.h>
-#include <AGESA.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-/*
- * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
- *
- * Lane Id
- * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
- * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
- * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
- * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
- * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
- * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
- * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
- * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
- * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
- * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
- * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
- * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
- * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
- * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
- * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
- * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
- * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
- * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
- * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
- * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
- * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
- * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
- * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
- * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
- * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
- * 25 DP0_TX[P,N]1
- * 26 DP0_TX[P,N]2
- * 27 DP0_TX[P,N]3
- * 28 DP1_TX[P,N]0
- * 29 DP1_TX[P,N]1
- * 30 DP1_TX[P,N]2
- * 31 DP1_TX[P,N]3
- * 32 DP2_TX[P,N]0
- * 33 DP2_TX[P,N]1
- * 34 DP2_TX[P,N]2
- * 35 DP2_TX[P,N]3
- * 36 DP2_TX[P,N]4
- * 37 DP2_TX[P,N]5
- * 38 DP2_TX[P,N]6
- */
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 1)
-	},
-	/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 1)
-	},
-	/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0)
-	},
-};
-
-/*
- * It is not known, if the setup is complete.
- *
- * Tested and works: VGA/DVI
- * Untested: HDMI
- */
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// DP0 to HDMI0/DP
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
-	},
-	// DP1 to FCH
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
-	},
-	// DP2 to HDMI1/DP
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
-{
-	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
-	FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-	FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
-}
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = {
-
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
-/*
-  TODO: is this OK for DDR3 socket FM2?
-  MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-  CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
-  ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
-  CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-  */
-  PSO_END
-};
-
-static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = {
-
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
-
-  PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	if (CONFIG(BOARD_ASUS_F2A85_M) || CONFIG(BOARD_ASUS_F2A85_M_PRO))
-		InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M;
-	else if (CONFIG(BOARD_ASUS_F2A85_M_LE))
-		InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M_LE;
-}
-
-void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
-{
-	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
-	InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
-}
diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl
deleted file mode 100644
index 494fc73201..0000000000
--- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* This file defines the processor and performance state capability
- * for each core in the system.  It is included into the DSDT for each
- * core.  It assumes that each core of the system has the same performance
- * characteristics.
-*/
-	/* P-state support: The maximum number of P-states supported by the */
-	/* CPUs we'll use is 6. */
-	/* Get from AMI BIOS. */
-	Name(_PSS, Package(){
-		Package()
-		{
-			0x00000D48,
-			0x00011170,
-			0x00000004,
-			0x00000004,
-			0x00000000,
-			0x00000000
-		},
-
-		Package()
-		{
-			0x00000AF0,
-			0x0000C544,
-			0x00000004,
-			0x00000004,
-			0x00000001,
-			0x00000001
-		},
-
-		Package()
-		{
-		    0x000009C4,
-		    0x0000B3B0,
-		    0x00000004,
-		    0x00000004,
-		    0x00000002,
-		    0x00000002
-		},
-
-		Package()
-		{
-		    0x00000898,
-		    0x0000ABE0,
-		    0x00000004,
-		    0x00000004,
-		    0x00000003,
-		    0x00000003
-		},
-
-		Package()
-		{
-		    0x00000708,
-		    0x0000A410,
-		    0x00000004,
-		    0x00000004,
-		    0x00000004,
-		    0x00000004
-		},
-
-		Package()
-		{
-		    0x00000578,
-		    0x00006F54,
-		    0x00000004,
-		    0x00000004,
-		    0x00000005,
-		    0x00000005
-		}
-	})
-
-	Name(_PCT, Package(){
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
-	})
-
-	Method(_PPC, 0){
-		Return(0)
-	}
diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl
deleted file mode 100644
index 30d10ce741..0000000000
--- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  General event 3  */
-	Method(_L03) {
-		/* DBGO("\\_GPE\\_L00\n") */
-	}
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl
deleted file mode 100644
index dc3f0e8e76..0000000000
--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl
+++ /dev/null
@@ -1,251 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-	/* Routing is in System Bus scope */
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - F15 Host Controller */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-		Package(){0x0001FFFF, 0, INTB, 0 },
-		Package(){0x0001FFFF, 1, INTC, 0 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-
-		/* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-#if CONFIG(BOARD_ASUS_F2A85_M_PRO)
-		Package(){0x000FFFFF, 0, INTA, 0 },
-		Package(){0x000FFFFF, 1, INTB, 0 },
-		Package(){0x000FFFFF, 2, INTC, 0 },
-		Package(){0x000FFFFF, 3, INTD, 0 },
-#endif /* CONFIG_BOARD_ASUS_F2A85_M_PRO */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
-		 *                            EHCI @ func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* SB devices */
-		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
-		Package(){0x0010FFFF, 0, INTC, 0 },
-		Package(){0x0010FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 21 PCIe Bridge */
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - F15 Host Controller */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-		Package(){0x0001FFFF, 0, 0, 17 },
-		Package(){0x0001FFFF, 1, 0, 18 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		Package(){0x0002FFFF, 1, 0, 19 },
-		Package(){0x0002FFFF, 2, 0, 16 },
-		Package(){0x0002FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-
-		/* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
-		 *                            EHCI @ func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
-		Package(){0x0010FFFF, 0, 0, 0x12},
-		Package(){0x0010FFFF, 1, 0, 0x11},
-
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 21 PCIE Bridge */
-		Package(){0x0015FFFF, 0, 0, 17 },
-		Package(){0x0015FFFF, 1, 0, 18 },
-		Package(){0x0015FFFF, 2, 0, 19 },
-		Package(){0x0015FFFF, 3, 0, 16 },
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	/* black slot */
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PBR0, Package(){
-		/* PCIx1 on SB */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(ABR0, Package(){
-		/* PCIx1 on SB */
-		Package(){0x0000FFFF, 0, 0, 0x10 },
-		Package(){0x0000FFFF, 1, 0, 0x11 },
-		Package(){0x0000FFFF, 2, 0, 0x12 },
-		Package(){0x0000FFFF, 3, 0, 0x13 },
-	})
-
-	Name(PBR1, Package(){
-		/* Onboard network */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(ABR1, Package(){
-		/* Onboard network */
-		Package(){0x0000FFFF, 0, 0, 0x11 },
-		Package(){0x0000FFFF, 1, 0, 0x12 },
-		Package(){0x0000FFFF, 2, 0, 0x13 },
-		Package(){0x0000FFFF, 3, 0, 0x10 },
-	})
-
-	/* SB PCI Bridge  */
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-	})
diff --git a/src/mainboard/asus/f2a85-m/acpi/sata.asl b/src/mainboard/asus/f2a85-m/acpi/sata.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/asus/f2a85-m/acpi/sata.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/asus/f2a85-m/acpi/sleep.asl b/src/mainboard/asus/f2a85-m/acpi/sleep.asl
deleted file mode 100644
index 07f6419b64..0000000000
--- a/src/mainboard/asus/f2a85-m/acpi/sleep.asl
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-
-	UPWS = 0x07
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/f2a85-m/acpi/superio.asl b/src/mainboard/asus/f2a85-m/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/asus/f2a85-m/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/asus/f2a85-m/acpi/thermal.asl b/src/mainboard/asus/f2a85-m/acpi/thermal.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/asus/f2a85-m/acpi/thermal.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl
deleted file mode 100644
index a5846fe848..0000000000
--- a/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
diff --git a/src/mainboard/asus/f2a85-m/board_info.txt b/src/mainboard/asus/f2a85-m/board_info.txt
deleted file mode 100644
index 091def6775..0000000000
--- a/src/mainboard/asus/f2a85-m/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_FM2/F2A85M/
-ROM package: DIP8
-ROM protocol: [http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64BV.htm SPI]
-ROM socketed: y
-Flashrom support: y
-Release year: 2013
diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c
deleted file mode 100644
index 1355453ce2..0000000000
--- a/src/mainboard/asus/f2a85-m/bootblock.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <device/pnp_type.h>
-#include <amdblocks/acpimmio.h>
-#include <stdint.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8728f/it8728f.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct6779d/nct6779d.h>
-
-static void sbxxx_enable_48mhzout(void)
-{
-	/* most likely programming to 48MHz out signal */
-	u32 reg32;
-	reg32 = misc_read32(0x28);
-	reg32 &= 0xffc7ffff;
-	reg32 |= 0x00100000;
-	misc_write32(0x28, reg32);
-
-	misc_write32(0x40, misc_read32(0x40) & (~0x80u));
-}
-
-static void superio_init_m(void)
-{
-	const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
-	const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
-
-	ite_kill_watchdog(gpio);
-	ite_enable_serial(uart, CONFIG_TTYS0_BASE);
-	ite_enable_3vsbsw(gpio);
-}
-
-static void superio_init_m_pro(void)
-{
-	const pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1);
-
-	nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE);
-}
-
-void bootblock_mainboard_early_init(void)
-{
-	/* enable SIO clock */
-	sbxxx_enable_48mhzout();
-
-	if (CONFIG(BOARD_ASUS_F2A85_M_PRO))
-		superio_init_m_pro();
-	else
-		superio_init_m();
-}
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
deleted file mode 100644
index b7e9c1b76a..0000000000
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <vendorcode/amd/agesa/f15tn/AGESA.h>
-
-/* Include the files that instantiate the configuration definitions. */
-#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
-/* AGESA nonsense: the next two headers depend on heapManager.h */
-#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
-/* These tables are optional and may be used to adjust memory timing settings */
-#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FM2_SOCKET_SUPPORT		TRUE
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_SODIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
-#define BLDOPT_REMOVE_SRAT			FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-#define BLDOPT_REMOVE_CRAT			TRUE
-
-/* Build configuration values here. */
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_CLOCK_SELECT		DDR1600_FREQUENCY
-#define BLDCFG_ENABLE_ECC_FEATURE		FALSE
-#define BLDCFG_ECC_SYNC_FLOOD			FALSE
-
-#define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
-#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
-
-#define BLDCFG_IOMMU_SUPPORT			TRUE
-
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-
-/* Customized OEM build configurations for FCH component */
-#define BLDCFG_FCH_GPP_LINK_CONFIG		PortA1B1C1D1
-#define BLDCFG_FCH_GPP_PORT0_PRESENT		TRUE
-#define BLDCFG_FCH_GPP_PORT1_PRESENT		TRUE
-#define BLDCFG_FCH_GPP_PORT2_PRESENT		CONFIG(BOARD_ASUS_F2A85_M_PRO)
-
-CONST GPIO_CONTROL f2a85_m_gpio[] = {
-	{-1}
-};
-#define BLDCFG_FCH_GPIO_CONTROL_LIST		(f2a85_m_gpio)
-
-/* Moving this include up will break AGESA. */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/asus/f2a85-m/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
deleted file mode 100644
index 08a74e8ac7..0000000000
--- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
+++ /dev/null
@@ -1,124 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family15tn/root_complex
-
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family15tn
-			device lapic 10 on end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-		chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
-
-			chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
-				device pci 0.0 on  end # Root Complex
-				device pci 0.2 on  end # IOMMU
-				device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
-				device pci 1.1 on  end # Internal Multimedia
-				device pci 2.0 on  end # PCIE SLOT0 x16 blue
-				device pci 3.0 off end # unused?
-				device pci 4.0 on  end # PCIE 4x black
-				device pci 5.0 off end # unused?
-				device pci 6.0 off end # unused?
-				device pci 7.0 off end # LAN
-				device pci 8.0 off end # NB/SB Link P2P bridge
-			end	#chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
-
-			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
-				device pci 10.0 on  end # XHCI HC0
-				device pci 10.1 on  end # XHCI HC1
-				device pci 11.0 on  end # SATA
-				device pci 12.0 on  end # USB
-				device pci 12.2 on  end # USB
-				device pci 13.0 on  end # USB
-				device pci 13.2 on  end # USB
-				device pci 14.0 on  end # SMBUS
-				device pci 14.1 off end # IDE	0x439c
-				device pci 14.2 on  end # HDA	0x4383
-				device pci 14.3 on      # LPC	0x439d
-					chip superio/ite/it8728f
-						register "TMPIN1.mode" = "THERMAL_RESISTOR"
-						register "TMPIN2.mode" = "THERMAL_RESISTOR"
-						register "TMPIN3.mode" = "THERMAL_RESISTOR"
-
-						register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
-						register "FAN1.smart.tmpin" = "1"
-						register "FAN1.smart.tmp_off" = "0x80" # never
-						register "FAN1.smart.tmp_start" = "20"
-						register "FAN1.smart.tmp_full" = "70"
-						register "FAN1.smart.tmp_delta" = "0"
-						register "FAN1.smart.smoothing" = "1"
-						register "FAN1.smart.pwm_start" = "20"
-						register "FAN1.smart.slope" = "32"
-
-						# Enable tacho reading for chassis fan.
-						register "FAN2.mode" = "FAN_MODE_OFF"
-
-						device pnp 2e.0 off #  Floppy
-							io 0x60 = 0x3f0
-							irq 0x70 = 6
-							drq 0x74 = 2
-						end
-						device pnp 2e.1 on #  Com1
-							io 0x60 = 0x3f8
-							irq 0x70 = 4
-						end
-						device pnp 2e.2 off #  Com2
-							io 0x60 = 0x2f8
-							irq 0x70 = 3
-						end
-						device pnp 2e.3 off #  Parallel Port
-							io 0x60 = 0x378
-							irq 0x70 = 7
-						end
-						device pnp 2e.4 on #  Env Controller
-							io 0x60 = 0x290
-							io 0x62 = 0x220
-							irq 0x70 = 0
-						end
-						device pnp 2e.5 on #  Keyboard
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1
-						end
-						device pnp 2e.6 off #  Mouse
-							irq 0x70 = 12
-						end
-						device pnp 2e.7 on #  GPIO
-							io 0x60 = 0x228 #SMI
-							io 0x62 = 0x300 #Simple I/O
-							io 0x64 = 0x238 #Phony resource IT8603E does not have it
-							irq 0x70 = 0
-						end
-						device pnp 2e.a off end #  CIR
-					end	#superio/ite/it8728f
-				end	#device pci 14.3 # LPC
-				device pci 14.4 on  end # PCI 0x4384
-				device pci 14.5 on  end # USB 2
-				device pci 14.6 off end # Gec
-				device pci 14.7 off end # SD
-				device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
-				device pci 15.1 on end # PCIe 1 onboard gigabit
-				device pci 15.2 off end # unused
-				device pci 15.3 off end # unused
-
-			end	#chip southbridge/amd/agesa/hudson
-
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end	#chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
-	end	#domain
-end	#chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb
deleted file mode 100644
index bc0dc42de4..0000000000
--- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb
+++ /dev/null
@@ -1,123 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family15tn/root_complex
-
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family15tn
-			device lapic 10 on end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-		chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
-
-			chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
-				device pci 0.0 on  end # Root Complex
-				device pci 0.2 on  end # IOMMU
-				device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
-				device pci 1.1 on  end # Internal Multimedia
-				device pci 2.0 on  end # PCIE SLOT0 x16 blue
-				device pci 3.0 off end # unused?
-				device pci 4.0 on  end # PCIE 4x black
-				device pci 5.0 off end # unused?
-				device pci 6.0 off end # unused?
-				device pci 7.0 off end # LAN
-				device pci 8.0 off end # NB/SB Link P2P bridge
-			end	#chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
-
-			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
-				device pci 10.0 on  end # XHCI HC0
-				device pci 10.1 on  end # XHCI HC1
-				device pci 11.0 on  end # SATA
-				device pci 12.0 on  end # USB
-				device pci 12.2 on  end # USB
-				device pci 13.0 on  end # USB
-				device pci 13.2 on  end # USB
-				device pci 14.0 on  end # SMBUS
-				device pci 14.1 off end # IDE	0x439c
-				device pci 14.2 on  end # HDA	0x4383
-				device pci 14.3 on      # LPC	0x439d
-					chip superio/ite/it8728f
-						register "TMPIN1.mode" = "THERMAL_RESISTOR"
-						register "TMPIN2.mode" = "THERMAL_RESISTOR"
-						register "TMPIN3.mode" = "THERMAL_RESISTOR"
-
-						register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
-						register "FAN1.smart.tmpin" = "1"
-						register "FAN1.smart.tmp_off" = "0x80" # never
-						register "FAN1.smart.tmp_start" = "20"
-						register "FAN1.smart.tmp_full" = "70"
-						register "FAN1.smart.tmp_delta" = "0"
-						register "FAN1.smart.smoothing" = "1"
-						register "FAN1.smart.pwm_start" = "20"
-						register "FAN1.smart.slope" = "32"
-
-						# Enable tacho reading for chassis fan.
-						register "FAN2.mode" = "FAN_MODE_OFF"
-
-						device pnp 2e.0 off #  Floppy
-							io 0x60 = 0x3f0
-							irq 0x70 = 6
-							drq 0x74 = 2
-						end
-						device pnp 2e.1 on #  Com1
-							io 0x60 = 0x3f8
-							irq 0x70 = 4
-						end
-						device pnp 2e.2 off #  Com2
-							io 0x60 = 0x2f8
-							irq 0x70 = 3
-						end
-						device pnp 2e.3 off #  Parallel Port
-							io 0x60 = 0x378
-							irq 0x70 = 7
-						end
-						device pnp 2e.4 on #  Env Controller
-							io 0x60 = 0x290
-							io 0x62 = 0x220
-							irq 0x70 = 0
-						end
-						device pnp 2e.5 on #  Keyboard
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1
-						end
-						device pnp 2e.6 off #  Mouse
-							irq 0x70 = 12
-						end
-						device pnp 2e.7 on #  GPIO
-							io 0x60 = 0x228 #SMI
-							io 0x62 = 0x300 #Simple I/O
-							io 0x64 = 0x238 #Phony resource IT8603E does not have it
-							irq 0x70 = 0
-						end
-						device pnp 2e.a off end #  CIR
-					end	#superio/ite/it8728f
-				end	#device pci 14.3 # LPC
-				device pci 14.4 on  end # PCI 0x4384
-				device pci 14.5 on  end # USB 2
-				device pci 14.6 off end # Gec
-				device pci 14.7 off end # SD
-				device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
-				device pci 15.1 on end # PCIe 1 onboard gigabit
-				device pci 15.2 off end # unused
-				device pci 15.3 off end # unused
-			end	#chip southbridge/amd/agesa/hudson
-
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end	#chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
-	end	#domain
-end	#chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
deleted file mode 100644
index 80582cbff3..0000000000
--- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
+++ /dev/null
@@ -1,136 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family15tn/root_complex
-
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family15tn
-			device lapic 10 on end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-		chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
-
-			chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
-				device pci 0.0 on  end # Root Complex
-				device pci 2.0 on  end # Internal Graphics P2P bridge 0x99XX
-			end	#chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
-
-			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
-				device pci 10.0 on  end # XHCI HC0
-				device pci 10.1 on  end # XHCI HC1
-				device pci 11.0 on  end # SATA
-				device pci 12.0 on  end # USB
-				device pci 12.2 on  end # USB
-				device pci 13.0 on  end # USB
-				device pci 13.2 on  end # USB
-				device pci 14.0 on  end # SMBUS
-				device pci 14.1 off end # unused
-				device pci 14.2 on  end # HDA	0x4383
-				device pci 14.3 on      # LPC	0x780e
-					chip superio/nuvoton/nct6779d
-						device pnp 2e.0 off end	# FDC
-						device pnp 2e.1 off end	# LPT1
-						device pnp 2e.2 on	#  COM1
-							io 0x60 = 0x3f8
-							irq 0x70 = 4
-						end
-						device pnp 2e.3 off end # COM2/IR
-						device pnp 2e.5 on      # Keyboard
-							io 0x60 = 0x0060        # KBC1 base
-							io 0x62 = 0x0064        # KBC2 base
-							irq 0x70 = 1
-							irq 0x72 = 12
-						end
-						device pnp 2e.6 off end # CIR
-						device pnp 2e.7 on	# GPIO6, GPIO7, GPIO8
-							irq 0xf4 = 0xff # GPIO6 i/o
-
-							irq 0xe0 = 0x7f # GPIO7 i/o
-							irq 0xe1 = 0x00 # GPIO7 data
-						end
-						device pnp 2e.008 off	# WDT1
-						end
-						device pnp 2e.108 on	# GPIO0, GPIO1
-							irq 0xe0 = 0xff # GPIO0 i/o
-							irq 0xe2 = 0xff # GPIO0 inversion
-							irq 0xe4 = 0xff # GPIO0 multiplex
-
-							irq 0xf0 = 0xff # GPIO1 i/o
-							irq 0xf4 = 0x08 # GPIO1 multiplex
-
-							irq 0xf5 = 0xff # WDT1 control mode
-							irq 0xf6 = 0x00 # WDT1 counter
-							irq 0xf7 = 0xff # WDT1 control / status
-						end
-						device pnp 2e.009 off	# GPIO8
-						end
-						device pnp 2e.109 on	# GPIO1
-						end
-						device pnp 2e.209 on	# GPIO2
-							irq 0xe0 = 0xff # GPIO2 i/o
-						end
-						device pnp 2e.309 on	# GPIO3
-							irq 0xe4 = 0x7f # GPIO3 i/o
-							irq 0xe5 = 0x00 # GPIO3 data
-						end
-						device pnp 2e.409 on	# GPIO4
-							irq 0xf0 = 0xff # GPIO4 i/o
-						end
-						device pnp 2e.509 on	# GPIO5
-							irq 0xf4 = 0xff # GPIO5 i/o
-						end
-						device pnp 2e.609 on	# GPIO6
-						end
-						device pnp 2e.709 on	# GPIO7
-						end
-						device pnp 2e.a on	# ACPI
-							irq 0xe6 = 0x4c
-							irq 0xe7 = 0x11
-							irq 0xf2 = 0x5d
-						end
-						device pnp 2e.b on	# Hardware Monitor, Front Panel LED
-							io  0x60 = 0x0290
-							io  0x62 = 0
-							io  0x70 = 0
-							irq 0xe2 = 0x7f
-							irq 0xe4 = 0xf1
-						end
-						device pnp 2e.d off end	# WDT1
-						device pnp 2e.e off end # CIR WAKE-UP
-						device pnp 2e.f on	# GPIO Push-pull/Open-drain selection
-							irq 0xe6 = 7f
-						end
-						device pnp 2e.14 on	# PORT80 UART
-							irq 0xe0 = 0x00
-						end
-						device pnp 2e.16 off end # Deep Sleep
-					end
-				end	#device pci 14.3 # LPC
-
-				device pci 14.4 on end # PCI bridge
-				device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806])
-				device pci 15.0 on end # PCI bridge
-				device pci 15.1 on end # PCI bridge
-				# FIXME: serial console stops working when enabling resources
-				# for 15.2, and payloads hang
-				device pci 15.2 off end # PCI bridge
-			end	#chip southbridge/amd/hudson
-
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end	#chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
-	end	#domain
-end	#chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl
deleted file mode 100644
index c3f4ba3ac8..0000000000
--- a/src/mainboard/asus/f2a85-m/dsdt.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001		/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	/* Describe the USB Overcurrent pins */
-	#include "acpi/usb_oc.asl"
-
-	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
-
-	/* Describe the processor tree (\_SB) */
-	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
-
-	/* Describe the supported Sleep States for this Southbridge */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
-	#include "acpi/sleep.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
-		#include "acpi/routing.asl"
-
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
-
-			/**
-			 * TODO: The devices listed here (SBR0 and SBR1) do not appear to
-			 *       be referenced anywhere and could possibly be removed.
-			 */
-			Device(SBR0) { /* PCIe 1x SB */
-				Name(_ADR, 0x00150000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PICM){ Return(ABR0) }   /* APIC mode */
-					Return (PBR0)              /* PIC mode  */
-				}
-			}
-
-			Device(SBR1) { /* Onboard network */
-				Name(_ADR, 0x00150001)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT, 0) {
-					If(PICM){ Return(ABR1) }   /* APIC mode */
-					Return (PBR1)              /* PIC mode  */
-				}
-			}
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
-
-	}   /* End Scope(_SB)  */
-
-	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
-
-	/* Define the General Purpose Events for the platform */
-	#include "acpi/gpe.asl"
-
-	/* Define the Thermal zones and methods for the platform */
-	#include "acpi/thermal.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c
deleted file mode 100644
index a0997f88c4..0000000000
--- a/src/mainboard/asus/f2a85-m/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <stdint.h>
-#include <string.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c
deleted file mode 100644
index 37bce31c80..0000000000
--- a/src/mainboard/asus/f2a85-m/mainboard.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static const u8 mainboard_picr_data[] = {
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F
-};
-static const u8 mainboard_intr_data[0x54] = {
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/*************************************************
- * enable the dedicated function in thatcher board.
- *************************************************/
-static void mainboard_enable(struct device *dev)
-{
-	msr_t msr;
-
-	pirq_setup();
-
-	msr = rdmsr(LS_CFG_MSR);
-	msr.lo &= ~(1 << 28);
-	wrmsr(LS_CFG_MSR, msr);
-
-	msr = rdmsr(DC_CFG_MSR);
-	msr.lo &= ~(1 << 4);
-	msr.lo &= ~(1 << 13);
-	wrmsr(DC_CFG_MSR, msr);
-
-	msr = rdmsr(BU_CFG_MSR);
-	msr.lo &= ~(1 << 23);
-	wrmsr(BU_CFG_MSR, msr);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
deleted file mode 100644
index 6b1c75ef50..0000000000
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/agesa/hudson/smbus.h>
-#include <stdint.h>
-
-void board_BeforeAgesa(struct sysinfo *cb)
-{
-	u8 byte;
-
-	post_code(0x30);
-
-	/* turn on secondary smbus at b20 */
-	pm_write8(0x28, pm_read8(0x28) | 1);
-
-	/* set DDR3 voltage */
-	byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
-
-	/* default is byte = 0x0, so no need to set it in this case */
-	if (byte)
-		do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
-}