diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-01 23:17:37 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:56:55 +0000 |
| commit | e56f0c7cab77b89a750b4a3f7f380b1a10cd0d1d (patch) | |
| tree | 8894438e7c7131dcadb7e01816a628d1e28564f6 /src/mainboard | |
| parent | 5e8e911b7caee021faff96c4e82a77a42544ea62 (diff) | |
mb/*/*: Remove AMD FAMILY15TN boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
164 files changed, 0 insertions, 10039 deletions
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c deleted file mode 100644 index b553203abe..0000000000 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <FchPlatform.h> - -#include "imc.h" - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * AMD Parmer Platform ALC272 Verb Table - */ -static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Parmer Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig deleted file mode 100644 index 515ffca56c..0000000000 --- a/src/mainboard/amd/parmer/Kconfig +++ /dev/null @@ -1,48 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_AMD_PARMER - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - select SOUTHBRIDGE_AMD_AGESA_HUDSON - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - default "amd/parmer" - -config MAINBOARD_PART_NUMBER - default "Parmer" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1002,9900" - -config HUDSON_LEGACY_FREE - bool - default y - -endif # BOARD_AMD_PARMER diff --git a/src/mainboard/amd/parmer/Kconfig.name b/src/mainboard/amd/parmer/Kconfig.name deleted file mode 100644 index 3aedc956ae..0000000000 --- a/src/mainboard/amd/parmer/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_PARMER - bool "Parmer" diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc deleted file mode 100644 index 549801d78f..0000000000 --- a/src/mainboard/amd/parmer/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c deleted file mode 100644 index 352ab25b4d..0000000000 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ /dev/null @@ -1,202 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> - -#include <northbridge/amd/agesa/state_machine.h> - -/* - * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) - * - * Lane Id - * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 - * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 - * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 - * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 - * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 - * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 - * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 - * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 - * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI - * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI - * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI - * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI - * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI - * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI - * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI - * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI - * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI - * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI - * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI - * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI - * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI - * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI - * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI - * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI - * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) - * 25 DP0_TX[P,N]1 - * 26 DP0_TX[P,N]2 - * 27 DP0_TX[P,N]3 - * 28 DP1_TX[P,N]0 - * 29 DP1_TX[P,N]1 - * 30 DP1_TX[P,N]2 - * 31 DP1_TX[P,N]3 - * 32 DP2_TX[P,N]0 - * 33 DP2_TX[P,N]1 - * 34 DP2_TX[P,N]2 - * 35 DP2_TX[P,N]3 - * 36 DP2_TX[P,N]4 - * 37 DP2_TX[P,N]5 - * 38 DP2_TX[P,N]6 - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, LAN */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl deleted file mode 100644 index 91bcabc52d..0000000000 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/parmer/acpi/mainboard.asl b/src/mainboard/amd/parmer/acpi/mainboard.asl deleted file mode 100644 index f7fc551df9..0000000000 --- a/src/mainboard/amd/parmer/acpi/mainboard.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - - /* AcpiGpe0Blk */ - OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, - } diff --git a/src/mainboard/amd/parmer/acpi/routing.asl b/src/mainboard/amd/parmer/acpi/routing.asl deleted file mode 100644 index a440d5fc62..0000000000 --- a/src/mainboard/amd/parmer/acpi/routing.asl +++ /dev/null @@ -1,306 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* SB devices */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 Pcie Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - }) diff --git a/src/mainboard/amd/parmer/acpi/sata.asl b/src/mainboard/amd/parmer/acpi/sata.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/amd/parmer/acpi/sata.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl deleted file mode 100644 index cd714cec87..0000000000 --- a/src/mainboard/amd/parmer/acpi/sleep.asl +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*CSSM = 1 - SSEN = 1*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\_SB.SBRI <= 0x13) { - * \_SB.PWDE = 0 - *} - */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 - - UPWS = 0x07 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - USBS = 1 - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/parmer/acpi/superio.asl b/src/mainboard/amd/parmer/acpi/superio.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/amd/parmer/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/parmer/acpi/thermal.asl b/src/mainboard/amd/parmer/acpi/thermal.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/amd/parmer/acpi/thermal.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/parmer/acpi/usb_oc.asl b/src/mainboard/amd/parmer/acpi/usb_oc.asl deleted file mode 100644 index a5846fe848..0000000000 --- a/src/mainboard/amd/parmer/acpi/usb_oc.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/parmer/board_info.txt b/src/mainboard/amd/parmer/board_info.txt deleted file mode 100644 index 4ed37bc829..0000000000 --- a/src/mainboard/amd/parmer/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: DB-FS1r2 (Parmer) -Category: eval -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/amd/parmer/bootblock.c b/src/mainboard/amd/parmer/bootblock.c deleted file mode 100644 index ccd8ec1b40..0000000000 --- a/src/mainboard/amd/parmer/bootblock.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> - -void bootblock_mainboard_early_init(void) -{ -} diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c deleted file mode 100644 index 319c811042..0000000000 --- a/src/mainboard/amd/parmer/buildOpts.c +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> - -/* Select the CPU family */ -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE - -/* Build configuration values here. */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_SYNC_FLOOD FALSE - -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ - -#define BLDCFG_IOMMU_SUPPORT FALSE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -CONST GPIO_CONTROL parmer_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (parmer_gpio) - -#include <PlatformInstall.h> diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout deleted file mode 100644 index a11e1dd0e6..0000000000 --- a/src/mainboard/amd/parmer/cmos.layout +++ /dev/null @@ -1,35 +0,0 @@ -#***************************************************************************** -# SPDX-License-Identifier: GPL-2.0-only - -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb deleted file mode 100644 index 1d11eef6b0..0000000000 --- a/src/mainboard/amd/parmer/devicetree.cb +++ /dev/null @@ -1,64 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 on end # PCIE Slot1 x1 - device pci 7.0 on end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn - - chip southbridge/amd/agesa/hudson - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SMBUS - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family15tn - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl deleted file mode 100644 index b3ebbf536f..0000000000 --- a/src/mainboard/amd/parmer/dsdt.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_SB) */ - #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - - /* Describe the supported Sleep States for this Southbridge */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ - #include "acpi/sleep.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End Scope(_SB) */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c deleted file mode 100644 index e5d576a349..0000000000 --- a/src/mainboard/amd/parmer/irq_tables.c +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <commonlib/bsd/helpers.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* PCI bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) - pirq->checksum = sum; - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c deleted file mode 100644 index 9c4ba53ca4..0000000000 --- a/src/mainboard/amd/parmer/mainboard.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static const u8 mainboard_picr_data[0x54] = { - 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F -}; -static const u8 mainboard_intr_data[0x54] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x11, 0x12, 0x13 -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/************************************************* - * enable the dedicated function in parmer board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c deleted file mode 100644 index 4dddaef54d..0000000000 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <FchPlatform.h> - -#include "imc.h" - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * AMD Thatcher Platform ALC272 Verb Table - */ -static const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig deleted file mode 100644 index 45b47ddaca..0000000000 --- a/src/mainboard/amd/thatcher/Kconfig +++ /dev/null @@ -1,49 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_AMD_THATCHER - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - select SOUTHBRIDGE_AMD_AGESA_HUDSON - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select SUPERIO_SMSC_LPC47N217 - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - default "amd/thatcher" - -config MAINBOARD_PART_NUMBER - default "Thatcher" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1002,9917" - -config HUDSON_LEGACY_FREE - bool - default y - -endif # BOARD_AMD_THATCHER diff --git a/src/mainboard/amd/thatcher/Kconfig.name b/src/mainboard/amd/thatcher/Kconfig.name deleted file mode 100644 index aff5246cc7..0000000000 --- a/src/mainboard/amd/thatcher/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_THATCHER - bool "Thatcher" diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc deleted file mode 100644 index 549801d78f..0000000000 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c deleted file mode 100644 index 23cda27728..0000000000 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ /dev/null @@ -1,202 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> - -#include <northbridge/amd/agesa/state_machine.h> - -/* - * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) - * - * Lane Id - * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 - * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 - * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 - * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 - * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 - * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 - * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 - * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 - * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI - * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI - * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI - * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI - * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI - * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI - * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI - * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI - * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI - * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI - * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI - * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI - * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI - * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI - * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI - * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI - * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) - * 25 DP0_TX[P,N]1 - * 26 DP0_TX[P,N]2 - * 27 DP0_TX[P,N]3 - * 28 DP1_TX[P,N]0 - * 29 DP1_TX[P,N]1 - * 30 DP1_TX[P,N]2 - * 31 DP1_TX[P,N]3 - * 32 DP2_TX[P,N]0 - * 33 DP2_TX[P,N]1 - * 34 DP2_TX[P,N]2 - * 35 DP2_TX[P,N]3 - * 36 DP2_TX[P,N]4 - * 37 DP2_TX[P,N]5 - * 38 DP2_TX[P,N]6 - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 15, 8), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, LAN */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, Disabled */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - // DP0 to HDMI0/DP0 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - // DP1 to HDMI1/DP1 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - // DP2 to MINI-DDI Card - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = FALSE; - FchReset->Xhci1Enable = FALSE; -} - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl deleted file mode 100644 index 494fc73201..0000000000 --- a/src/mainboard/amd/thatcher/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package() - { - 0x00000D48, - 0x00011170, - 0x00000004, - 0x00000004, - 0x00000000, - 0x00000000 - }, - - Package() - { - 0x00000AF0, - 0x0000C544, - 0x00000004, - 0x00000004, - 0x00000001, - 0x00000001 - }, - - Package() - { - 0x000009C4, - 0x0000B3B0, - 0x00000004, - 0x00000004, - 0x00000002, - 0x00000002 - }, - - Package() - { - 0x00000898, - 0x0000ABE0, - 0x00000004, - 0x00000004, - 0x00000003, - 0x00000003 - }, - - Package() - { - 0x00000708, - 0x0000A410, - 0x00000004, - 0x00000004, - 0x00000004, - 0x00000004 - }, - - Package() - { - 0x00000578, - 0x00006F54, - 0x00000004, - 0x00000004, - 0x00000005, - 0x00000005 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl deleted file mode 100644 index 91bcabc52d..0000000000 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/thatcher/acpi/mainboard.asl b/src/mainboard/amd/thatcher/acpi/mainboard.asl deleted file mode 100644 index f7fc551df9..0000000000 --- a/src/mainboard/amd/thatcher/acpi/mainboard.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - - /* AcpiGpe0Blk */ - OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, - } diff --git a/src/mainboard/amd/thatcher/acpi/routing.asl b/src/mainboard/amd/thatcher/acpi/routing.asl deleted file mode 100644 index a440d5fc62..0000000000 --- a/src/mainboard/amd/thatcher/acpi/routing.asl +++ /dev/null @@ -1,306 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* SB devices */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 Pcie Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - }) diff --git a/src/mainboard/amd/thatcher/acpi/sata.asl b/src/mainboard/amd/thatcher/acpi/sata.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/amd/thatcher/acpi/sata.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl deleted file mode 100644 index e09a638607..0000000000 --- a/src/mainboard/amd/thatcher/acpi/sleep.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*CSSM = 1 - SSEN = 1*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\_SB.SBRI <= 0x13) { - * \_SB.PWDE = 0 - *} - */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 - - UPWS = 0x07 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* clear USB wake up signal */ - USBS = 1 - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/thatcher/acpi/superio.asl b/src/mainboard/amd/thatcher/acpi/superio.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/amd/thatcher/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/thatcher/acpi/thermal.asl b/src/mainboard/amd/thatcher/acpi/thermal.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/amd/thatcher/acpi/thermal.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/thatcher/acpi/usb_oc.asl b/src/mainboard/amd/thatcher/acpi/usb_oc.asl deleted file mode 100644 index a5846fe848..0000000000 --- a/src/mainboard/amd/thatcher/acpi/usb_oc.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/thatcher/board_info.txt b/src/mainboard/amd/thatcher/board_info.txt deleted file mode 100644 index e0ff2e31a9..0000000000 --- a/src/mainboard/amd/thatcher/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: DB-FP2 (Thatcher) -Category: eval -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c deleted file mode 100644 index c086709fcd..0000000000 --- a/src/mainboard/amd/thatcher/bootblock.c +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <amdblocks/acpimmio_legacy_gpio100.h> -#include <bootblock_common.h> -#include <console/console.h> -#include <superio/smsc/lpc47n217/lpc47n217.h> - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) - -void bootblock_mainboard_early_init(void) -{ - post_code(0x30); - post_code(0x31); - - gpio_100_write8(0x1, 0x98); - - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - pm_write8(0xea, 0x1); - - lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c deleted file mode 100644 index 5f21d2e2f9..0000000000 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> - -/* Select the CPU family */ -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE - -/* Build configuration values here. */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_SYNC_FLOOD FALSE - -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ - -#define BLDCFG_IOMMU_SUPPORT FALSE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -#define FCH_NO_XHCI_SUPPORT TRUE - -CONST GPIO_CONTROL thatcher_gpio[] = { - {183, Function1, PullUpB}, - {-1} -}; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (thatcher_gpio) - -#include <PlatformInstall.h> diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout deleted file mode 100644 index a11e1dd0e6..0000000000 --- a/src/mainboard/amd/thatcher/cmos.layout +++ /dev/null @@ -1,35 +0,0 @@ -#***************************************************************************** -# SPDX-License-Identifier: GPL-2.0-only - -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb deleted file mode 100644 index 3f7b190689..0000000000 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ /dev/null @@ -1,79 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x8 - device pci 3.0 off end - device pci 4.0 on end # LAN - device pci 5.0 on end # PCIE MINI0 - device pci 6.0 on end # PCIE MINI1 - device pci 7.0 off end - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn - - chip southbridge/amd/agesa/hudson - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SMBUS - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/lpc47n217 - device pnp 2e.3 off # Parallel - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end #chip superio/smsc/lpc47n217 - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family15tn - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl deleted file mode 100644 index b3ebbf536f..0000000000 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_SB) */ - #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - - /* Describe the supported Sleep States for this Southbridge */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ - #include "acpi/sleep.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End Scope(_SB) */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c deleted file mode 100644 index e5d576a349..0000000000 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <commonlib/bsd/helpers.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* PCI bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) - pirq->checksum = sum; - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c deleted file mode 100644 index 7c31d216c2..0000000000 --- a/src/mainboard/amd/thatcher/mainboard.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> - -static const u8 mainboard_picr_data[] = { - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F -}; -static const u8 mainboard_intr_data[0x54] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x11, 0x12, 0x13 -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/************************************************* - * enable the dedicated function in thatcher board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - msr_t msr; - - pirq_setup(); - - msr = rdmsr(LS_CFG_MSR); - msr.lo &= ~(1 << 28); - wrmsr(LS_CFG_MSR, msr); - - msr = rdmsr(DC_CFG_MSR); - msr.lo &= ~(1 << 4); - msr.lo &= ~(1 << 13); - wrmsr(DC_CFG_MSR, msr); - - msr = rdmsr(BU_CFG_MSR); - msr.lo &= ~(1 << 23); - wrmsr(BU_CFG_MSR, msr); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c deleted file mode 100644 index 24a7208e3b..0000000000 --- a/src/mainboard/asus/a88xm-e/BiosCallOuts.c +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> - -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * ASUS A88XM-E board ALC887-VD Verb Table - * - * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running - * the vendor BIOS. - */ -const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { - {0x11, 0x90460130}, - {0x12, 0x40330000}, - {0x14, 0x01014010}, - {0x15, 0x411111f0}, - {0x16, 0x411111f0}, - {0x17, 0x411111f0}, - {0x18, 0x01a19040}, - {0x19, 0x02a19050}, - {0x1a, 0x0181304f}, - {0x1b, 0x02214020}, - {0x1c, 0x411111f0}, - {0x1d, 0x4044c601}, - {0x1e, 0x411111f0}, - {0x1f, 0x411111f0} -}; - -static const CODEC_TBL_LIST CodecTableList[] = { - {0x10ec0887, (CODEC_ENTRY *)&a88xm_e_alc887_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY *)0x0FFFFFFFFUL} -}; - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - /* Fan Control */ - FchParams_env->Imc.ImcEnable = FALSE; - FchParams_env->Hwm.HwMonitorEnable = FALSE; - FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ -} diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig deleted file mode 100644 index 56dddebcdb..0000000000 --- a/src/mainboard/asus/a88xm-e/Kconfig +++ /dev/null @@ -1,57 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_ASUS_A88XM_E - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - select SOUTHBRIDGE_AMD_AGESA_HUDSON - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select SUPERIO_ITE_IT8728F - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -config MAINBOARD_DIR - default "asus/a88xm-e" - -config MAINBOARD_PART_NUMBER - default "A88XM-E" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config HUDSON_XHCI_FWM - bool - default n - -config HUDSON_IMC_FWM - bool - default n - -config IRQ_SLOT_COUNT - int - default 11 - -config VGA_BIOS_ID - string - default "1002,990e" - -config HUDSON_XHCI_ENABLE - bool - default n - -config HUDSON_LEGACY_FREE - bool - default n - -endif # BOARD_ASUS_A88XM_E diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name deleted file mode 100644 index 492d6109ee..0000000000 --- a/src/mainboard/asus/a88xm-e/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_A88XM_E - bool "A88XM-E" diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc deleted file mode 100644 index 549801d78f..0000000000 --- a/src/mainboard/asus/a88xm-e/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c deleted file mode 100644 index aa880e7bee..0000000000 --- a/src/mainboard/asus/a88xm-e/OemCustomize.c +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <Porting.h> -#include <AGESA.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - -/* - * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) - * - * Lane Id - * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 - * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 - * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 - * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 - * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 - * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 - * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 - * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 - * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI - * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI - * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI - * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI - * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI - * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI - * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI - * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI - * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI - * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI - * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI - * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI - * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI - * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI - * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI - * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI - * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) - * 25 DP0_TX[P,N]1 - * 26 DP0_TX[P,N]2 - * 27 DP0_TX[P,N]3 - * 28 DP1_TX[P,N]0 - * 29 DP1_TX[P,N]1 - * 30 DP1_TX[P,N]2 - * 31 DP1_TX[P,N]3 - * 32 DP2_TX[P,N]0 - * 33 DP2_TX[P,N]1 - * 34 DP2_TX[P,N]2 - * 35 DP2_TX[P,N]3 - * 36 DP2_TX[P,N]4 - * 37 DP2_TX[P,N]5 - * 38 DP2_TX[P,N]6 - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, -}; - -/* - * It is not known, if the setup is complete. - * - * Tested and works: VGA/DVI, HDMI - */ -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - // DP0 to HDMI0/DP - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) - }, - // DP1 to FCH - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - // DP2 to HDMI1/DP - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/* CUSTOMER OVERRIDES MEMORY TABLE */ -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ - -static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = { - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl deleted file mode 100644 index 35583de49f..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. - */ - -/* - * P-state support: the maximum number of P-states supported - * by the CPUs that we'll use - is 6. Taken from AMI BIOS. - */ -Name(_PSS, Package(){ - Package() - { - 0x00000D48, - 0x00011170, - 0x00000004, - 0x00000004, - 0x00000000, - 0x00000000 - }, - - Package() - { - 0x00000AF0, - 0x0000C544, - 0x00000004, - 0x00000004, - 0x00000001, - 0x00000001 - }, - - Package() - { - 0x000009C4, - 0x0000B3B0, - 0x00000004, - 0x00000004, - 0x00000002, - 0x00000002 - }, - - Package() - { - 0x00000898, - 0x0000ABE0, - 0x00000004, - 0x00000004, - 0x00000003, - 0x00000003 - }, - - Package() - { - 0x00000708, - 0x0000A410, - 0x00000004, - 0x00000004, - 0x00000004, - 0x00000004 - }, - - Package() - { - 0x00000578, - 0x00006F54, - 0x00000004, - 0x00000004, - 0x00000005, - 0x00000005 - } -}) - -Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} -}) - -Method(_PPC, 0){ - Return(0) -} diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl deleted file mode 100644 index 9f01c7a0ca..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/gpe.asl +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - } - - /* Legacy PM event */ - Method(_L08) { - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - } - - /* USB controller PME# */ - Method(_L0B) { - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl deleted file mode 100644 index 99511c5a21..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/routing.asl +++ /dev/null @@ -1,246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - - /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - - * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB - */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* SB devices */ - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - - /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - - * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB - */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 17 }, - Package(){0x0015FFFF, 1, 0, 18 }, - Package(){0x0015FFFF, 2, 0, 19 }, - Package(){0x0015FFFF, 3, 0, 16 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - /* black slot */ - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PBR0, Package(){ - /* PCIx1 on SB */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(ABR0, Package(){ - /* PCIx1 on SB */ - Package(){0x0000FFFF, 0, 0, 0x10 }, - Package(){0x0000FFFF, 1, 0, 0x11 }, - Package(){0x0000FFFF, 2, 0, 0x12 }, - Package(){0x0000FFFF, 3, 0, 0x13 }, - }) - - Name(PBR1, Package(){ - /* Onboard network */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(ABR1, Package(){ - /* Onboard network */ - Package(){0x0000FFFF, 0, 0, 0x11 }, - Package(){0x0000FFFF, 1, 0, 0x12 }, - Package(){0x0000FFFF, 2, 0, 0x13 }, - Package(){0x0000FFFF, 3, 0, 0x10 }, - }) - - /* SB PCI Bridge */ - Name(PCIB, Package(){ - /* PCI slots: slot 0 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - }) diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/sata.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/si.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl deleted file mode 100644 index 46f37f344e..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/sleep.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ -Method(\_PTS, 1) { - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 - - UPWS = 0x07 -} /* End Method(\_PTS) */ - -/* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ -Method(\_WAK, 1) { - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/thermal.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl deleted file mode 100644 index d90fffdd40..0000000000 --- a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt deleted file mode 100644 index 579dce634d..0000000000 --- a/src/mainboard/asus/a88xm-e/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: https://www.asus.com/Motherboards/A88XME/ -ROM package: DIP8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y (without AmdSpiRomProtect modules) -Release year: 2014 diff --git a/src/mainboard/asus/a88xm-e/bootblock.c b/src/mainboard/asus/a88xm-e/bootblock.c deleted file mode 100644 index 0bc8d2e15e..0000000000 --- a/src/mainboard/asus/a88xm-e/bootblock.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <bootblock_common.h> -#include <device/pnp_type.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> - -static void sbxxx_enable_48mhzout(void) -{ - /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ - u32 reg32; - reg32 = misc_read32(0x28); - reg32 &= ~(7 << 19); - reg32 |= (2 << 19); - misc_write32(0x28, reg32); - - /* Enable Auxiliary OSCOUT2 */ - misc_write32(0x40, misc_read32(0x40) & ~(1 << 7)); -} - -static void superio_init_m(void) -{ - const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); - const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); - - ite_kill_watchdog(gpio); - ite_enable_serial(uart, CONFIG_TTYS0_BASE); - ite_enable_3vsbsw(gpio); -} - -void bootblock_mainboard_early_init(void) -{ - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - superio_init_m(); -} diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c deleted file mode 100644 index 363e31f96d..0000000000 --- a/src/mainboard/asus/a88xm-e/buildOpts.c +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> - -/* Include the files that instantiate the configuration definitions. */ -#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> -/* AGESA nonsense: the next two headers depend on heapManager.h */ -#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> -/* These tables are optional and may be used to adjust memory timing settings */ -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - -/* Select the CPU family */ -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FM2_SOCKET_SUPPORT TRUE - -#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE - -/* Build configuration values here. */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP - -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_ENABLE_ECC_FEATURE FALSE -#define BLDCFG_ECC_SYNC_FLOOD FALSE - -#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto - -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ - -#define BLDCFG_IOMMU_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE - -/* Customized OEM build configurations for FCH component */ -#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 -#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE -#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE -#define BLDCFG_FCH_GPP_PORT2_PRESENT TRUE - -CONST GPIO_CONTROL a88xm_e_gpio[] = { - {-1} -}; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (a88xm_e_gpio) - -/* Moving this include up will break AGESA. */ -#include <PlatformInstall.h> diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout deleted file mode 100644 index efaa386acd..0000000000 --- a/src/mainboard/asus/a88xm-e/cmos.layout +++ /dev/null @@ -1,37 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/a88xm-e/devicetree.cb b/src/mainboard/asus/a88xm-e/devicetree.cb deleted file mode 100644 index f427d0d88b..0000000000 --- a/src/mainboard/asus/a88xm-e/devicetree.cb +++ /dev/null @@ -1,113 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia (iGPU Audio) - device pci 2.0 on end # PCIEX16 - device pci 3.0 off end # - - device pci 4.0 off end # PCIe x4 (?) - device pci 5.0 off end # PCIe x1 (?) - device pci 6.0 off end # PCIe x1 (?) - device pci 7.0 off end # PCIe x1 (?) - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA AHCI - device pci 12.0 on end # USB OHCI - device pci 12.2 on end # USB EHCI - device pci 13.0 on end # USB OHCI - device pci 13.2 on end # USB EHCI - device pci 14.0 on end # SMBUS - device pci 14.1 off end # IDE - device pci 14.2 on end # HDA - device pci 14.3 on # LPC - chip superio/ite/it8728f - register "TMPIN1.mode" = "THERMAL_RESISTOR" - register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN3.mode" = "THERMAL_RESISTOR" - - register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = "1" - register "FAN1.smart.tmp_off" = "0x80" # never - register "FAN1.smart.tmp_start" = "20" - register "FAN1.smart.tmp_full" = "70" - register "FAN1.smart.tmp_delta" = "0" - register "FAN1.smart.smoothing" = "1" - register "FAN1.smart.pwm_start" = "20" - register "FAN1.smart.slope" = "32" - - # Enable tacho reading for chassis fan. - register "FAN2.mode" = "FAN_MODE_OFF" - - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off end # COM2 - device pnp 2e.3 off end # Parallel Port - device pnp 2e.4 on # Env Controller - io 0x60 = 0x290 - io 0x62 = 0x220 - irq 0x70 = 0 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x228 # SMI - io 0x62 = 0x300 # Simple I/O - io 0x64 = 0 # Phony resource IT8603E does not have it - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI bridge - device pci 14.5 on end # USB OHCI - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 on end # PCIe RP0: PCIEX1_1 - device pci 15.1 off end # PCIe RP1: - - device pci 15.2 on end # PCIe RP2: Onboard Ethernet - device pci 15.3 off end # PCIe RP3: - - end #chip southbridge/amd/agesa/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */ - { {0xA0, 0x00}, {0xA2, 0x00}, }, - }" - - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl deleted file mode 100644 index 97e2d754e7..0000000000 --- a/src/mainboard/asus/a88xm-e/dsdt.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_PR) */ - #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - - /* Describe the supported Sleep States for this Southbridge */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ - #include "acpi/sleep.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End Scope(_SB) */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" - -} -/* End of ASL file */ diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c deleted file mode 100644 index 7ca1c4b951..0000000000 --- a/src/mainboard/asus/a88xm-e/irq_tables.c +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <string.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->slots); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - { - const u8 *const v = (u8 *)(pirq); - for (i = 0; i < pirq->size; i++) - sum += v[i]; - } - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) - pirq->checksum = sum; - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c deleted file mode 100644 index 800364062a..0000000000 --- a/src/mainboard/asus/a88xm-e/mainboard.c +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <device/device.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static const u8 mainboard_picr_data[] = { - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, -}; -static const u8 mainboard_intr_data[84] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/* dedicated "enable" function (taken from thatcher) */ -static void mainboard_enable(struct device *dev) -{ - msr_t msr; - - pirq_setup(); - - msr = rdmsr(LS_CFG_MSR); - /* Enable streaming store functionality. */ - msr.lo &= ~(1 << 28); - wrmsr(LS_CFG_MSR, msr); - - msr = rdmsr(DC_CFG_MSR); - /* Enable speculative TLB preloads. */ - msr.lo &= ~(1 << 4); - /* Enable the DC hardware prefetcher. */ - msr.lo &= ~(1 << 13); - wrmsr(DC_CFG_MSR, msr); - - msr = rdmsr(BU_CFG_MSR); - /* Disable the L2 way lock. */ - msr.lo &= ~(1 << 23); - wrmsr(BU_CFG_MSR, msr); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c deleted file mode 100644 index 4a966a99cf..0000000000 --- a/src/mainboard/asus/a88xm-e/mptable.c +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\ - bus_isa, (intr), (apicid), (pin)) - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ - (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - } - - /* PCIe Lan */ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /* Local Ints: Type IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c deleted file mode 100644 index a25195539a..0000000000 --- a/src/mainboard/asus/a88xm-e/romstage.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/smbus.h> - -static void smbus_setup(void) -{ - post_code(0x30); - - /* turn on secondary smbus at b20 */ - pm_write8(0x28, pm_read8(0x28) | 0x01); -} - -void board_BeforeAgesa(struct sysinfo *cb) -{ - smbus_setup(); -} diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c deleted file mode 100644 index a426f01bfa..0000000000 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> - -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * ASUS F2A85-M board ALC887-VD Verb Table - * - * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running - * the vendor BIOS. - */ -#if !CONFIG(BOARD_ASUS_F2A85_M_LE) -const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = { - {0x11, 0x99430140}, - {0x12, 0x411111f0}, - {0x14, 0x01014010}, - {0x15, 0x01011012}, - {0x16, 0x01016011}, - {0x17, 0x01012014}, - {0x18, 0x01a19850}, - {0x19, 0x02a19c60}, - {0x1a, 0x0181305f}, - {0x1b, 0x02214c20}, - {0x1c, 0x411111f0}, - {0x1d, 0x4005e601}, - {0x1e, 0x01456130}, - {0x1f, 0x411111f0}, - {0xff, 0xffffffff} -}; -#else -const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = { - {0x11, 0x99430140}, - {0x12, 0x411111f0}, - {0x14, 0x01014010}, - {0x15, 0x411111f0}, - {0x16, 0x411111f0}, - {0x17, 0x411111f0}, - {0x18, 0x01a19850}, - {0x19, 0x02a19c60}, - {0x1a, 0x0181305f}, - {0x1b, 0x02214c20}, - {0x1c, 0x411111f0}, - {0x1d, 0x4004c601}, - {0x1e, 0x01456130}, - {0x1f, 0x411111f0}, - {0xff, 0xffffffff} -}; -#endif - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - /* Fan Control */ - FchParams_env->Imc.ImcEnable = FALSE; - FchParams_env->Hwm.HwMonitorEnable = FALSE; - FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ -} diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig deleted file mode 100644 index a2e4f60341..0000000000 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ /dev/null @@ -1,105 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - select SOUTHBRIDGE_AMD_AGESA_HUDSON - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE - select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO - select SUPERIO_NUVOTON_COMMON_COM_A if BOARD_ASUS_F2A85_M_PRO - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -choice - prompt "DDR3 memory voltage" - default BOARD_ASUS_F2A85_M_DDR3_VOLT_150 - -config BOARD_ASUS_F2A85_M_DDR3_VOLT_135 - bool "1.35V" - help - Set DRR3 memory voltage to 1.35V -config BOARD_ASUS_F2A85_M_DDR3_VOLT_150 - bool "1.50V" - help - Set DRR3 memory voltage to 1.50V -config BOARD_ASUS_F2A85_M_DDR3_VOLT_165 - bool "1.65V" - help - Set DRR3 memory voltage to 1.65V -endchoice - -config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL - hex - default 0x9e if BOARD_ASUS_F2A85_M_DDR3_VOLT_135 - default 0x0 if BOARD_ASUS_F2A85_M_DDR3_VOLT_150 - default 0x1e if BOARD_ASUS_F2A85_M_DDR3_VOLT_165 - -config MAINBOARD_DIR - default "asus/f2a85-m" - -config MAINBOARD_PART_NUMBER - default "F2A85-M" if BOARD_ASUS_F2A85_M - default "F2A85-M_LE" if BOARD_ASUS_F2A85_M_LE - default "F2A85-M_PRO" if BOARD_ASUS_F2A85_M_PRO - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config HUDSON_XHCI_FWM - bool - default n - -config HUDSON_IMC_FWM - bool - default n - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO - -config VGA_BIOS_ID - string - default "1002,9993" - -config HUDSON_LEGACY_FREE - bool - default n - -config POST_IO - bool - default n - -endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO - -if BOARD_ASUS_F2A85_M_LE - -config VGA_BIOS_ID - string - default "1002,9901" - -endif - -config DEVICETREE - default "devicetree_f2a85-m_pro.cb" if BOARD_ASUS_F2A85_M_PRO - default "devicetree_f2a85-m.cb" if BOARD_ASUS_F2A85_M - default "devicetree_f2a85-m_le.cb" if BOARD_ASUS_F2A85_M_LE - -endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE diff --git a/src/mainboard/asus/f2a85-m/Kconfig.name b/src/mainboard/asus/f2a85-m/Kconfig.name deleted file mode 100644 index 8a3d7ef1d1..0000000000 --- a/src/mainboard/asus/f2a85-m/Kconfig.name +++ /dev/null @@ -1,8 +0,0 @@ -config BOARD_ASUS_F2A85_M - bool "F2A85-M" - -config BOARD_ASUS_F2A85_M_PRO - bool "F2A85-M PRO" - -config BOARD_ASUS_F2A85_M_LE - bool "F2A85-M LE" diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc deleted file mode 100644 index 549801d78f..0000000000 --- a/src/mainboard/asus/f2a85-m/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c deleted file mode 100644 index 930f1fcca2..0000000000 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <Porting.h> -#include <AGESA.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - -/* - * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) - * - * Lane Id - * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 - * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 - * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 - * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 - * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 - * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 - * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 - * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 - * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI - * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI - * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI - * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI - * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI - * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI - * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI - * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI - * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI - * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI - * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI - * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI - * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI - * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI - * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI - * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI - * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) - * 25 DP0_TX[P,N]1 - * 26 DP0_TX[P,N]2 - * 27 DP0_TX[P,N]3 - * 28 DP1_TX[P,N]0 - * 29 DP1_TX[P,N]1 - * 30 DP1_TX[P,N]2 - * 31 DP1_TX[P,N]3 - * 32 DP2_TX[P,N]0 - * 33 DP2_TX[P,N]1 - * 34 DP2_TX[P,N]2 - * 35 DP2_TX[P,N]3 - * 36 DP2_TX[P,N]4 - * 37 DP2_TX[P,N]5 - * 38 DP2_TX[P,N]6 - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, -}; - -/* - * It is not known, if the setup is complete. - * - * Tested and works: VGA/DVI - * Untested: HDMI - */ -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - // DP0 to HDMI0/DP - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) - }, - // DP1 to FCH - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - // DP2 to HDMI1/DP - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = { - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), -/* - TODO: is this OK for DDR3 socket FM2? - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - */ - PSO_END -}; - -static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = { - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - if (CONFIG(BOARD_ASUS_F2A85_M) || CONFIG(BOARD_ASUS_F2A85_M_PRO)) - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M; - else if (CONFIG(BOARD_ASUS_F2A85_M_LE)) - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M_LE; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl deleted file mode 100644 index 494fc73201..0000000000 --- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package() - { - 0x00000D48, - 0x00011170, - 0x00000004, - 0x00000004, - 0x00000000, - 0x00000000 - }, - - Package() - { - 0x00000AF0, - 0x0000C544, - 0x00000004, - 0x00000004, - 0x00000001, - 0x00000001 - }, - - Package() - { - 0x000009C4, - 0x0000B3B0, - 0x00000004, - 0x00000004, - 0x00000002, - 0x00000002 - }, - - Package() - { - 0x00000898, - 0x0000ABE0, - 0x00000004, - 0x00000004, - 0x00000003, - 0x00000003 - }, - - Package() - { - 0x00000708, - 0x0000A410, - 0x00000004, - 0x00000004, - 0x00000004, - 0x00000004 - }, - - Package() - { - 0x00000578, - 0x00006F54, - 0x00000004, - 0x00000004, - 0x00000005, - 0x00000005 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl deleted file mode 100644 index 30d10ce741..0000000000 --- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl deleted file mode 100644 index dc3f0e8e76..0000000000 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ /dev/null @@ -1,251 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - - /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - -#if CONFIG(BOARD_ASUS_F2A85_M_PRO) - Package(){0x000FFFFF, 0, INTA, 0 }, - Package(){0x000FFFFF, 1, INTB, 0 }, - Package(){0x000FFFFF, 2, INTC, 0 }, - Package(){0x000FFFFF, 3, INTD, 0 }, -#endif /* CONFIG_BOARD_ASUS_F2A85_M_PRO */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* SB devices */ - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - - /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 17 }, - Package(){0x0015FFFF, 1, 0, 18 }, - Package(){0x0015FFFF, 2, 0, 19 }, - Package(){0x0015FFFF, 3, 0, 16 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - /* black slot */ - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PBR0, Package(){ - /* PCIx1 on SB */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(ABR0, Package(){ - /* PCIx1 on SB */ - Package(){0x0000FFFF, 0, 0, 0x10 }, - Package(){0x0000FFFF, 1, 0, 0x11 }, - Package(){0x0000FFFF, 2, 0, 0x12 }, - Package(){0x0000FFFF, 3, 0, 0x13 }, - }) - - Name(PBR1, Package(){ - /* Onboard network */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(ABR1, Package(){ - /* Onboard network */ - Package(){0x0000FFFF, 0, 0, 0x11 }, - Package(){0x0000FFFF, 1, 0, 0x12 }, - Package(){0x0000FFFF, 2, 0, 0x13 }, - Package(){0x0000FFFF, 3, 0, 0x10 }, - }) - - /* SB PCI Bridge */ - Name(PCIB, Package(){ - /* PCI slots: slot 0 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - }) diff --git a/src/mainboard/asus/f2a85-m/acpi/sata.asl b/src/mainboard/asus/f2a85-m/acpi/sata.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/asus/f2a85-m/acpi/sata.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/f2a85-m/acpi/sleep.asl b/src/mainboard/asus/f2a85-m/acpi/sleep.asl deleted file mode 100644 index 07f6419b64..0000000000 --- a/src/mainboard/asus/f2a85-m/acpi/sleep.asl +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*CSSM = 1 - SSEN = 1*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\_SB.SBRI <= 0x13) { - * \_SB.PWDE = 0 - *} - */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 - - UPWS = 0x07 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/asus/f2a85-m/acpi/superio.asl b/src/mainboard/asus/f2a85-m/acpi/superio.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/asus/f2a85-m/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/f2a85-m/acpi/thermal.asl b/src/mainboard/asus/f2a85-m/acpi/thermal.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/asus/f2a85-m/acpi/thermal.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl deleted file mode 100644 index a5846fe848..0000000000 --- a/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/asus/f2a85-m/board_info.txt b/src/mainboard/asus/f2a85-m/board_info.txt deleted file mode 100644 index 091def6775..0000000000 --- a/src/mainboard/asus/f2a85-m/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: http://www.asus.com/Motherboards/AMD_Socket_FM2/F2A85M/ -ROM package: DIP8 -ROM protocol: [http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64BV.htm SPI] -ROM socketed: y -Flashrom support: y -Release year: 2013 diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c deleted file mode 100644 index 1355453ce2..0000000000 --- a/src/mainboard/asus/f2a85-m/bootblock.c +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pnp_type.h> -#include <amdblocks/acpimmio.h> -#include <stdint.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6779d/nct6779d.h> - -static void sbxxx_enable_48mhzout(void) -{ - /* most likely programming to 48MHz out signal */ - u32 reg32; - reg32 = misc_read32(0x28); - reg32 &= 0xffc7ffff; - reg32 |= 0x00100000; - misc_write32(0x28, reg32); - - misc_write32(0x40, misc_read32(0x40) & (~0x80u)); -} - -static void superio_init_m(void) -{ - const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); - const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); - - ite_kill_watchdog(gpio); - ite_enable_serial(uart, CONFIG_TTYS0_BASE); - ite_enable_3vsbsw(gpio); -} - -static void superio_init_m_pro(void) -{ - const pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1); - - nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE); -} - -void bootblock_mainboard_early_init(void) -{ - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - if (CONFIG(BOARD_ASUS_F2A85_M_PRO)) - superio_init_m_pro(); - else - superio_init_m(); -} diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c deleted file mode 100644 index b7e9c1b76a..0000000000 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> - -/* Include the files that instantiate the configuration definitions. */ -#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> -/* AGESA nonsense: the next two headers depend on heapManager.h */ -#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> -/* These tables are optional and may be used to adjust memory timing settings */ -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - -/* Select the CPU family */ -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FM2_SOCKET_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE - -/* Build configuration values here. */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY -#define BLDCFG_ENABLE_ECC_FEATURE FALSE -#define BLDCFG_ECC_SYNC_FLOOD FALSE - -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ - -#define BLDCFG_IOMMU_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE - -/* Customized OEM build configurations for FCH component */ -#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 -#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE -#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE -#define BLDCFG_FCH_GPP_PORT2_PRESENT CONFIG(BOARD_ASUS_F2A85_M_PRO) - -CONST GPIO_CONTROL f2a85_m_gpio[] = { - {-1} -}; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (f2a85_m_gpio) - -/* Moving this include up will break AGESA. */ -#include <PlatformInstall.h> diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout deleted file mode 100644 index a11e1dd0e6..0000000000 --- a/src/mainboard/asus/f2a85-m/cmos.layout +++ /dev/null @@ -1,35 +0,0 @@ -#***************************************************************************** -# SPDX-License-Identifier: GPL-2.0-only - -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb deleted file mode 100644 index 08a74e8ac7..0000000000 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb +++ /dev/null @@ -1,124 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 blue - device pci 3.0 off end # unused? - device pci 4.0 on end # PCIE 4x black - device pci 5.0 off end # unused? - device pci 6.0 off end # unused? - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SMBUS - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - register "TMPIN1.mode" = "THERMAL_RESISTOR" - register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN3.mode" = "THERMAL_RESISTOR" - - register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = "1" - register "FAN1.smart.tmp_off" = "0x80" # never - register "FAN1.smart.tmp_start" = "20" - register "FAN1.smart.tmp_full" = "70" - register "FAN1.smart.tmp_delta" = "0" - register "FAN1.smart.smoothing" = "1" - register "FAN1.smart.pwm_start" = "20" - register "FAN1.smart.slope" = "32" - - # Enable tacho reading for chassis fan. - register "FAN2.mode" = "FAN_MODE_OFF" - - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0x290 - io 0x62 = 0x220 - irq 0x70 = 0 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x228 #SMI - io 0x62 = 0x300 #Simple I/O - io 0x64 = 0x238 #Phony resource IT8603E does not have it - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 on end # PCIe 0 - onboard PCIe 1x - device pci 15.1 on end # PCIe 1 onboard gigabit - device pci 15.2 off end # unused - device pci 15.3 off end # unused - - end #chip southbridge/amd/agesa/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb deleted file mode 100644 index bc0dc42de4..0000000000 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb +++ /dev/null @@ -1,123 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 blue - device pci 3.0 off end # unused? - device pci 4.0 on end # PCIE 4x black - device pci 5.0 off end # unused? - device pci 6.0 off end # unused? - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SMBUS - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - register "TMPIN1.mode" = "THERMAL_RESISTOR" - register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN3.mode" = "THERMAL_RESISTOR" - - register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = "1" - register "FAN1.smart.tmp_off" = "0x80" # never - register "FAN1.smart.tmp_start" = "20" - register "FAN1.smart.tmp_full" = "70" - register "FAN1.smart.tmp_delta" = "0" - register "FAN1.smart.smoothing" = "1" - register "FAN1.smart.pwm_start" = "20" - register "FAN1.smart.slope" = "32" - - # Enable tacho reading for chassis fan. - register "FAN2.mode" = "FAN_MODE_OFF" - - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0x290 - io 0x62 = 0x220 - irq 0x70 = 0 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x228 #SMI - io 0x62 = 0x300 #Simple I/O - io 0x64 = 0x238 #Phony resource IT8603E does not have it - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 on end # PCIe 0 - onboard PCIe 1x - device pci 15.1 on end # PCIe 1 onboard gigabit - device pci 15.2 off end # unused - device pci 15.3 off end # unused - end #chip southbridge/amd/agesa/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb deleted file mode 100644 index 80582cbff3..0000000000 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ /dev/null @@ -1,136 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 2.0 on end # Internal Graphics P2P bridge 0x99XX - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SMBUS - device pci 14.1 off end # unused - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x780e - chip superio/nuvoton/nct6779d - device pnp 2e.0 off end # FDC - device pnp 2e.1 off end # LPT1 - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off end # COM2/IR - device pnp 2e.5 on # Keyboard - io 0x60 = 0x0060 # KBC1 base - io 0x62 = 0x0064 # KBC2 base - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - irq 0xf4 = 0xff # GPIO6 i/o - - irq 0xe0 = 0x7f # GPIO7 i/o - irq 0xe1 = 0x00 # GPIO7 data - end - device pnp 2e.008 off # WDT1 - end - device pnp 2e.108 on # GPIO0, GPIO1 - irq 0xe0 = 0xff # GPIO0 i/o - irq 0xe2 = 0xff # GPIO0 inversion - irq 0xe4 = 0xff # GPIO0 multiplex - - irq 0xf0 = 0xff # GPIO1 i/o - irq 0xf4 = 0x08 # GPIO1 multiplex - - irq 0xf5 = 0xff # WDT1 control mode - irq 0xf6 = 0x00 # WDT1 counter - irq 0xf7 = 0xff # WDT1 control / status - end - device pnp 2e.009 off # GPIO8 - end - device pnp 2e.109 on # GPIO1 - end - device pnp 2e.209 on # GPIO2 - irq 0xe0 = 0xff # GPIO2 i/o - end - device pnp 2e.309 on # GPIO3 - irq 0xe4 = 0x7f # GPIO3 i/o - irq 0xe5 = 0x00 # GPIO3 data - end - device pnp 2e.409 on # GPIO4 - irq 0xf0 = 0xff # GPIO4 i/o - end - device pnp 2e.509 on # GPIO5 - irq 0xf4 = 0xff # GPIO5 i/o - end - device pnp 2e.609 on # GPIO6 - end - device pnp 2e.709 on # GPIO7 - end - device pnp 2e.a on # ACPI - irq 0xe6 = 0x4c - irq 0xe7 = 0x11 - irq 0xf2 = 0x5d - end - device pnp 2e.b on # Hardware Monitor, Front Panel LED - io 0x60 = 0x0290 - io 0x62 = 0 - io 0x70 = 0 - irq 0xe2 = 0x7f - irq 0xe4 = 0xf1 - end - device pnp 2e.d off end # WDT1 - device pnp 2e.e off end # CIR WAKE-UP - device pnp 2e.f on # GPIO Push-pull/Open-drain selection - irq 0xe6 = 7f - end - device pnp 2e.14 on # PORT80 UART - irq 0xe0 = 0x00 - end - device pnp 2e.16 off end # Deep Sleep - end - end #device pci 14.3 # LPC - - device pci 14.4 on end # PCI bridge - device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806]) - device pci 15.0 on end # PCI bridge - device pci 15.1 on end # PCI bridge - # FIXME: serial console stops working when enabling resources - # for 15.2, and payloads hang - device pci 15.2 off end # PCI bridge - end #chip southbridge/amd/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl deleted file mode 100644 index c3f4ba3ac8..0000000000 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_SB) */ - #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - - /* Describe the supported Sleep States for this Southbridge */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ - #include "acpi/sleep.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - - /** - * TODO: The devices listed here (SBR0 and SBR1) do not appear to - * be referenced anywhere and could possibly be removed. - */ - Device(SBR0) { /* PCIe 1x SB */ - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(ABR0) } /* APIC mode */ - Return (PBR0) /* PIC mode */ - } - } - - Device(SBR1) { /* Onboard network */ - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT, 0) { - If(PICM){ Return(ABR1) } /* APIC mode */ - Return (PBR1) /* PIC mode */ - } - } - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End Scope(_SB) */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c deleted file mode 100644 index a0997f88c4..0000000000 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/pirq_routing.h> -#include <console/console.h> -#include <commonlib/bsd/helpers.h> -#include <device/pci_def.h> -#include <stdint.h> -#include <string.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c deleted file mode 100644 index 37bce31c80..0000000000 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <device/device.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static const u8 mainboard_picr_data[] = { - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F -}; -static const u8 mainboard_intr_data[0x54] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x11, 0x12, 0x13 -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/************************************************* - * enable the dedicated function in thatcher board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - msr_t msr; - - pirq_setup(); - - msr = rdmsr(LS_CFG_MSR); - msr.lo &= ~(1 << 28); - wrmsr(LS_CFG_MSR, msr); - - msr = rdmsr(DC_CFG_MSR); - msr.lo &= ~(1 << 4); - msr.lo &= ~(1 << 13); - wrmsr(DC_CFG_MSR, msr); - - msr = rdmsr(BU_CFG_MSR); - msr.lo &= ~(1 << 23); - wrmsr(BU_CFG_MSR, msr); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c deleted file mode 100644 index 6b1c75ef50..0000000000 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/smbus.h> -#include <stdint.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u8 byte; - - post_code(0x30); - - /* turn on secondary smbus at b20 */ - pm_write8(0x28, pm_read8(0x28) | 1); - - /* set DDR3 voltage */ - byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - - /* default is byte = 0x0, so no need to set it in this case */ - if (byte) - do_smbus_write_byte(0xb20, 0x15, 0x3, byte); -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c deleted file mode 100644 index 1fb15968c1..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> - -#include <southbridge/amd/agesa/hudson/imc.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * AMD Parmer Platform ALC272 Verb Table - */ -static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = { - {0x10ec0272, (CODEC_ENTRY *)&Parmer_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY *)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig deleted file mode 100644 index fd185cdb52..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ /dev/null @@ -1,49 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_HP_PAVILION_M6_1035DX - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - select SOUTHBRIDGE_AMD_AGESA_HUDSON - select DEFAULT_POST_ON_LPC - select EC_COMPAL_ENE932 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - select NO_UART_ON_SUPERIO - -config MAINBOARD_DIR - default "hp/pavilion_m6_1035dx" - -config MAINBOARD_PART_NUMBER - default "Pavilion m6 1035dx" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1002,9900" - -endif # BOARD_HP_PAVILION_M6_1035DX diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name deleted file mode 100644 index a736970395..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_HP_PAVILION_M6_1035DX - bool "Pavilion m6 1035dx" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc deleted file mode 100644 index 5d42edabf4..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c -ramstage-y += ec.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c deleted file mode 100644 index b6cdc867ae..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ /dev/null @@ -1,205 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <Porting.h> -#include <AGESA.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - - -/* - * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) - * - * Lane Id - * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 - * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 - * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 - * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 - * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 - * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 - * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 - * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 - * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI - * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI - * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI - * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI - * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI - * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI - * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI - * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI - * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI - * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI - * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI - * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI - * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI - * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI - * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI - * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI - * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) - * 25 DP0_TX[P,N]1 - * 26 DP0_TX[P,N]2 - * 27 DP0_TX[P,N]3 - * 28 DP1_TX[P,N]0 - * 29 DP1_TX[P,N]1 - * 30 DP1_TX[P,N]2 - * 31 DP1_TX[P,N]3 - * 32 DP2_TX[P,N]0 - * 33 DP2_TX[P,N]1 - * 34 DP2_TX[P,N]2 - * 35 DP2_TX[P,N]3 - * 36 DP2_TX[P,N]4 - * 37 DP2_TX[P,N]5 - * 38 DP2_TX[P,N]6 - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, LAN */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform - * information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). - * If PlatformSpecificTable is populated, AGESA will base its settings on the - * data from the table. Otherwise, it will use its default conservative settings - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl deleted file mode 100644 index 59868a9882..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* Defines EC bits specific to the mainboard, needed by EC ASL */ -#include "mainboard.h" - -/* ACPI code for EC functions */ -#include <ec/compal/ene932/acpi/ec.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl deleted file mode 100644 index ff760b3380..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - Printf ("USB PME") - /* Notify devices of wake event */ - Notify(\_SB.PCI0.UOH1, 0x02) - Notify(\_SB.PCI0.UOH2, 0x02) - Notify(\_SB.PCI0.UOH3, 0x02) - Notify(\_SB.PCI0.UOH4, 0x02) - Notify(\_SB.PCI0.XHC0, 0x02) - Notify(\_SB.PCI0.UEH1, 0x02) - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* Lid switch opened or closed */ - Method(_L16) { - Printf ("Lid status changed") - /* Flip trigger polarity */ - LPOL = ~LPOL - /* Notify lid object of status change */ - Notify(\_SB.LID, 0x80) - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - Printf ("PCI bridge wake event") - /* Notify PCI bridges of wake event */ - Notify(\_SB.PCI0.PBR4, 0x02) - Notify(\_SB.PCI0.PBR5, 0x02) - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl deleted file mode 100644 index 467a4f56de..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - - /* AcpiGpe0Blk */ - OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, - } - - /* GPIO control block -- hardcoded to 0xfed80100 by AGESA */ - OperationRegion (GPIO, SystemMemory, 0xfed80100, 0x100) - Field (GPIO, ByteAcc, NoLock, Preserve) { - Offset (0x39), - , 6, - GP57, 1, /* out: WLAN control (rf-kill) */ - Offset (0x76), - , 7, - GE22, 1, /* General event 22 - connected to lid switch */ - } - - /* SMI/SCI control block -- hardcoded to 0xfed80200 by AGESA */ - OperationRegion (SMIX, SystemMemory, 0xfed80200, 0x100) - Field (SMIX, AnyAcc, NoLock, Preserve) { - Offset (0x08), /* SCI level: 0 = active low, 1 = active high */ - , 22, - LPOL, 1, /* SCI22 trigger polarity - lid switch */ - } - - /* - * Used by EC code on certain events - * - * From ec/compal/ene932/acpi/ec.asl: - * The mainboard must define a PNOT method to handle power state - * notifications and Notify CPU device objects to re-evaluate their - * _PPC and _CST tables. - */ - Method (PNOT) - { - Printf ("Received PNOT call (probably from EC)") - /* TODO: Implement this */ - } - -Scope (\_SB) { - Device (LID) - { - Name(_HID, EisaId("PNP0C0D")) - Name(_PRW, Package () {EC_LID_GPE, 0x04}) /* wake from S1-S4 */ - Method(_LID, 0) - { - Return (GE22) /* GE pin 22 */ - } - - Method (_INI, 0) - { - /* Make sure lid trigger polarity is set so that we - * trigger an SCI when lid status changes. - */ - LPOL = ~GE22 - } - } - - Device (MB) { - Name(_HID, EisaId("PNP0C01")) // System Board - - /* Lid open */ - Method (LIDO) { /* Stub */ } - /* Lid closed */ - Method (LIDC) { /* Stub */ } - /* Increase brightness */ - Method (BRTU) { /* Stub */ } - /* Decrease brightness */ - Method (BRTD) { /* Stub */ } - /* Switch display */ - Method (DSPS) { /* Stub */ } - /* Toggle wireless */ - Method (WLTG) - { - GP57 = ~GP57 - } - /* Return lid state */ - Method (LIDS) - { - Return(GE22) - } - } -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl deleted file mode 100644 index bf6a881405..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl +++ /dev/null @@ -1,311 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* SB devices */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - }) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/sata.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/sata.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/sata.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl deleted file mode 100644 index cd714cec87..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*CSSM = 1 - SSEN = 1*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\_SB.SBRI <= 0x13) { - * \_SB.PWDE = 0 - *} - */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 - - UPWS = 0x07 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - USBS = 1 - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/superio.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/superio.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/thermal.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/thermal.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/thermal.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl deleted file mode 100644 index a5846fe848..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/board_info.txt b/src/mainboard/hp/pavilion_m6_1035dx/board_info.txt deleted file mode 100644 index 4601a4aaba..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: laptop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Release year: 2012 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c deleted file mode 100644 index 377e39016b..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "mainboard.h" - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> - -/* Include the files that instantiate the configuration definitions. */ -#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> -/* AGESA nonsense: the next two headers depend on heapManager.h */ -#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> -/* These tables are optional and may be used to adjust memory timing settings */ -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - -/* Select the CPU family */ -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE - -/* Build configuration values here. */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_SYNC_FLOOD FALSE - -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ - -#define BLDCFG_IOMMU_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE - -/* - * The GPIO control is not well documented in AGESA, but is in the BKDG - * - * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route - * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1 - * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs - * are mostly in Function1, sometimes Function2. - * - * Note that the GpioOut bit does not mean that the GPIO is an output. That bit - * actually controls the output value, so GpioOut means "default to set". - * PullUpB is an inverted logic, so setting this bit means we're actually - * disabling the internal pull-up. The PullDown bit is NOT inverted logic. - * The output driver can be disabled with the GpioOutEnB bit, which is again, - * inverted logic. To make the list more readable, we define a few local macros - * to state what we mean. - */ -#define OUTPUT_HIGH (GpioOut) -#define OUTPUT_LOW (0) -#define INPUT (GpioOutEnB) -#define PULL_UP (0) -#define PULL_DOWN (PullDown | PullUpB) -#define PULL_NONE (PullUpB) - -CONST GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { - {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */ - {-1} -}; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (pavilion_m6_1035dx_gpio) - -/* - * These definitions could be moved to a common Hudson header, should we decide - * to provide our own, saner SCI mapping function - */ -#define GEVENT_PIN(gpe) ((gpe) + 0x40) -#define SCI_MAP_OHCI_12_0 0x58 -#define SCI_MAP_OHCI_13_0 0x59 -#define SCI_MAP_XHCI_10_0 0x78 -#define SCI_MAP_PWRBTN 0x73 - -CONST SCI_MAP_CONTROL m6_1035dx_sci_map[] = { - {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, - {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, - {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, - {SCI_MAP_OHCI_12_0, PME_GPE}, - {SCI_MAP_OHCI_13_0, PME_GPE}, - {SCI_MAP_XHCI_10_0, PME_GPE}, - {SCI_MAP_PWRBTN, PME_GPE}, -}; -#define BLDCFG_FCH_SCI_MAP_LIST (m6_1035dx_sci_map) - -/* - * Process the options... - * This file include MUST occur AFTER the user option selection settings. - * AGESA nonsense: Moving this include up will break AGESA. - */ -#include <PlatformInstall.h> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/cmos.default b/src/mainboard/hp/pavilion_m6_1035dx/cmos.default deleted file mode 100644 index b159660aa8..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/cmos.default +++ /dev/null @@ -1,4 +0,0 @@ -boot_option=Fallback -debug_level=Debug -nmi=Disable -power_on_after_fail=Disable diff --git a/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout b/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout deleted file mode 100644 index 1f3fc0a38a..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout +++ /dev/null @@ -1,43 +0,0 @@ -entries - -#start-bit length config config-ID name - -# RTC_BOOT_BYTE (coreboot hardcoded) -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter - -# southbridge/amd/agesa/hudson should use this but it doesn't -400 1 e 1 power_on_after_fail - -# The only option that is actually used -412 4 e 6 debug_level - -# southbridge/amd/agesa/hudson should use this but it doesn't -444 1 e 1 nmi - -984 16 h 0 check_sum - -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb deleted file mode 100644 index 5496a8a3f9..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ /dev/null @@ -1,65 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn - - chip southbridge/amd/agesa/hudson - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end - end - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family15tn - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl deleted file mode 100644 index 689c3e611b..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "mainboard.h" - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_SB) */ - #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - - /* Describe the supported Sleep States for this Southbridge */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ - #include "acpi/sleep.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End Scope(_SB) */ - - Scope(\_SB.PCI0.LIBR) { - #include "acpi/ec.asl" - } - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.c b/src/mainboard/hp/pavilion_m6_1035dx/ec.c deleted file mode 100644 index a96ab8e7ff..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include "ec.h" -#include <ec/compal/ene932/ec.h> - -/* The keyboard matrix tells the EC how the keyboard is wired internally */ -static void set_keyboard_matrix_us(void) -{ - ec_kbc_write_cmd(0x59); - ec_kbc_write_ib(0xE5); -} - -/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */ -static void enter_apm_mode(void) -{ - ec_kbc_write_cmd(0x59); - ec_kbc_write_ib(0xE9); -} - -void pavilion_m6_1035dx_ec_init(void) -{ - set_keyboard_matrix_us(); - - /* - * The EC has a special "blinking Caps Lock LED" mode which it normally - * enters when it believes the OS is not responding. It occasionally - * disables battery charging when in this mode, although other - * functionality is unaffected. Although the EC starts in APM mode by - * default, it only leaves the "blinking Caps Lock LED" mode after - * receiving the following command. - */ - enter_apm_mode(); -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h deleted file mode 100644 index b59cd60033..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H -#define _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H - -#include "mainboard.h" - -void pavilion_m6_1035dx_ec_init(void); - -#endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c deleted file mode 100644 index 36caea97de..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/pirq_routing.h> -#include <console/console.h> -#include <commonlib/bsd/helpers.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c deleted file mode 100644 index d85ab2e8a1..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "ec.h" - -#include <acpi/acpi.h> -#include <cpu/x86/smm.h> -#include <device/device.h> -#include <southbridge/amd/common/amd_pci_util.h> - -#include <southbridge/amd/agesa/hudson/smi.h> - -static const u8 mainboard_picr_data[0x54] = { - 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F -}; -static const u8 mainboard_intr_data[0x54] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x11, 0x12, 0x13 -}; - -static void pavilion_cold_boot_init(void) -{ - /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ - hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, SMI_LVL_LOW); - /* EC is not powered off during S3 sleep */ - pavilion_m6_1035dx_ec_init(); -} - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -static void mainboard_enable(struct device *dev) -{ - pirq_setup(); - - hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); - global_smi_enable(); - - if (!acpi_is_wakeup_s3()) - pavilion_cold_boot_init(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h deleted file mode 100644 index 531fdd2d99..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * "The way things are connected" and a few setup options - */ - -#ifndef _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H -#define _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H - -/* What is connected to GEVENT pins */ -#define EC_SCI_GEVENT 3 -#define EC_LID_GEVENT 22 -#define EC_SMI_GEVENT 23 -#define PCIE_GEVENT 8 - -/* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but - * we make the distinction between GEVENT pin and SCI. - */ -#define EC_SCI_GPE EC_SCI_GEVENT -#define EC_LID_GPE EC_LID_GEVENT -#define PME_GPE 0x0b -#define PCIE_GPE 0x18 - -#endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/smihandler.c b/src/mainboard/hp/pavilion_m6_1035dx/smihandler.c deleted file mode 100644 index fa81b280ee..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/smihandler.c +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * SMI handler -- mostly takes care of SMIs from the EC - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <ec/compal/ene932/ec.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <southbridge/amd/agesa/hudson/smi.h> - -#include "ec.h" - -#define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10) - -enum sleep_states { - S0 = 0, - S1 = 1, - S3 = 3, - S4 = 4, - S5 = 5, -}; - -enum ec_smi_event { - EC_SMI_EVENT_IDLE = 0x80, - EC_SMI_BATTERY_LOW = 0xb3, -}; - -/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */ -static void ec_enter_apm_mode(void) -{ - ec_kbc_write_cmd(0x59); - ec_kbc_write_ib(0xE9); -} -/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs */ -static void ec_enter_acpi_mode(void) -{ - ec_kbc_write_cmd(0x59); - ec_kbc_write_ib(0xE8); -} - -static uint8_t ec_get_smi_event(void) -{ - ec_kbc_write_cmd(0x56); - return ec_kbc_read_ob(); -} - -static void ec_process_smi(uint8_t src) -{ - /* Reading the SMI source satisfies the EC in terms of responding to - * the event, regardless of whether we take an action or not. - */ - - switch (src) { - case EC_SMI_BATTERY_LOW: - printk(BIOS_DEBUG, "Battery low. Shutting down\n"); - outl(ACPI_PM1_CNT_SLEEP(S5), ACPI_PM1_CNT_BLK); - break; - default: - printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src); - } -} - -static void handle_ec_smi(void) -{ - uint8_t src; - - while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE) - ec_process_smi(src); -} - -static void handle_lid_smi(void) -{ - /* Only triggered in non-ACPI mode on lid close. */ - outl(ACPI_PM1_CNT_SLEEP(S4), ACPI_PM1_CNT_BLK); -} - -int mainboard_smi_apmc(uint8_t data) -{ - switch (data) { - case ACPI_SMI_CMD_ENABLE: - printk(BIOS_DEBUG, "Enable ACPI mode\n"); - ec_enter_acpi_mode(); - hudson_disable_gevent_smi(EC_LID_GEVENT); - break; - case ACPI_SMI_CMD_DISABLE: - printk(BIOS_DEBUG, "Disable ACPI mode\n"); - ec_enter_apm_mode(); - hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, - SMI_LVL_LOW); - break; - default: - printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data); - } - return 0; -} - -void mainboard_smi_gpi(uint32_t gpi_sts) -{ - if (gpi_sts & (1 << EC_SMI_GEVENT)) - handle_ec_smi(); - if (gpi_sts & (1 << EC_LID_GEVENT)) - handle_lid_smi(); -} diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c deleted file mode 100644 index dd4c42b968..0000000000 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> - -#include <southbridge/amd/agesa/hudson/imc.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * AMD Parmer Platform ALC272 Verb Table - */ -static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig deleted file mode 100644 index dbf8b68253..0000000000 --- a/src/mainboard/lenovo/g505s/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_LENOVO_G505S - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - select SOUTHBRIDGE_AMD_AGESA_HUDSON - select DEFAULT_POST_ON_LPC - select EC_COMPAL_ENE932 - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - select NO_UART_ON_SUPERIO - -config MAINBOARD_DIR - default "lenovo/g505s" - -config MAINBOARD_PART_NUMBER - default "LENOVO G505S" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1002,990b" - -config PAYLOAD_CONFIGFILE - string - default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS - -endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/Kconfig.name b/src/mainboard/lenovo/g505s/Kconfig.name deleted file mode 100644 index ff3ca28e9b..0000000000 --- a/src/mainboard/lenovo/g505s/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_G505S - bool "AMD G505s" diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc deleted file mode 100644 index 5d42edabf4..0000000000 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c -ramstage-y += ec.c diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c deleted file mode 100644 index 80daf19afe..0000000000 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ /dev/null @@ -1,204 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <Porting.h> -#include <AGESA.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - -/* - * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) - * - * Lane Id - * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 - * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 - * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 - * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 - * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 - * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 - * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 - * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 - * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI - * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI - * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI - * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI - * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI - * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI - * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI - * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI - * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI - * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI - * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI - * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI - * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI - * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI - * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI - * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI - * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) - * 25 DP0_TX[P,N]1 - * 26 DP0_TX[P,N]2 - * 27 DP0_TX[P,N]3 - * 28 DP1_TX[P,N]0 - * 29 DP1_TX[P,N]1 - * 30 DP1_TX[P,N]2 - * 31 DP1_TX[P,N]3 - * 32 DP2_TX[P,N]0 - * 33 DP2_TX[P,N]1 - * 34 DP2_TX[P,N]2 - * 35 DP2_TX[P,N]3 - * 36 DP2_TX[P,N]4 - * 37 DP2_TX[P,N]5 - * 38 DP2_TX[P,N]6 - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, LAN */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform - * information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). - * If PlatformSpecificTable is populated, AGESA will base its settings on the - * data from the table. Otherwise, it will use its default conservative settings - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/lenovo/g505s/acpi/ec.asl b/src/mainboard/lenovo/g505s/acpi/ec.asl deleted file mode 100644 index cde03fac2c..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/ec.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* Defines EC bits specific to the mainboard, needed by EC ASL */ -#include "../mainboard.h" - -/* ACPI code for EC functions */ -#include <ec/compal/ene932/acpi/ec.asl> diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl deleted file mode 100644 index 74b4c4807b..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - Printf ("USB PME") - /* Notify devices of wake event */ - Notify(\_SB.PCI0.UOH1, 0x02) - Notify(\_SB.PCI0.UOH2, 0x02) - Notify(\_SB.PCI0.UOH3, 0x02) - Notify(\_SB.PCI0.UOH4, 0x02) - Notify(\_SB.PCI0.XHC0, 0x02) - Notify(\_SB.PCI0.UEH1, 0x02) - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* Lid switch opened or closed */ - Method(_L16) { - Printf ("Lid status changed") - /* Flip trigger polarity */ - LPOL = ~LPOL - /* Notify lid object of status change */ - Notify(\_SB.LID, 0x80) - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - Printf ("PCI bridge wake event") - /* Notify PCI bridges of wake event */ - Notify(\_SB.PCI0.PBR4, 0x02) - Notify(\_SB.PCI0.PBR5, 0x02) - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl deleted file mode 100644 index 36f82a3335..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* AcpiGpe0Blk */ - OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, - } - - /* GPIO control block -- hardcoded to 0xfed80100 by AGESA */ - OperationRegion (GPIO, SystemMemory, 0xfed80100, 0x100) - Field (GPIO, ByteAcc, NoLock, Preserve) { - Offset (0x39), - , 6, - GP57, 1, /* out: WLAN control (rf-kill) */ - Offset (0x76), - , 7, - GE22, 1, /* General event 22 - connected to lid switch */ - } - - /* SMI/SCI control block -- hardcoded to 0xfed80200 by AGESA */ - OperationRegion (SMIX, SystemMemory, 0xfed80200, 0x100) - Field (SMIX, AnyAcc, NoLock, Preserve) { - Offset (0x08), /* SCI level: 0 = active low, 1 = active high */ - , 22, - LPOL, 1, /* SCI22 trigger polarity - lid switch */ - } - - /* - * Used by EC code on certain events - * - * From ec/compal/ene932/acpi/ec.asl: - * The mainboard must define a PNOT method to handle power state - * notifications and Notify CPU device objects to re-evaluate their - * _PPC and _CST tables. - */ - Method (PNOT) - { - Printf ("Received PNOT call (probably from EC)") - /* TODO: Implement this */ - } - -Scope (\_SB) { - Device (LID) - { - Name(_HID, EisaId("PNP0C0D")) - Name(_PRW, Package () {EC_LID_GPE, 0x04}) /* wake from S1-S4 */ - Method(_LID, 0) - { - Return (GE22) /* GE pin 22 */ - } - - Method (_INI, 0) - { - /* Make sure lid trigger polarity is set so that we - * trigger an SCI when lid status changes. - */ - LPOL = ~GE22 - } - } - - Device (MB) { - Name(_HID, EisaId("PNP0C01")) // System Board - - /* Lid open */ - Method (LIDO) { /* Stub */ } - /* Lid closed */ - Method (LIDC) { /* Stub */ } - /* Increase brightness */ - Method (BRTU) { /* Stub */ } - /* Decrease brightness */ - Method (BRTD) { /* Stub */ } - /* Switch display */ - Method (DSPS) { /* Stub */ } - /* Toggle wireless */ - Method (WLTG) - { - GP57 = ~GP57 - } - /* Return lid state */ - Method (LIDS) - { - Return(GE22) - } - } -} diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl deleted file mode 100644 index 6f91672106..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* SB devices */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PS6, Package(){ - }) - Name(APS6, Package(){ - }) - Name(PS7, Package(){ - }) - Name(APS7, Package(){ - }) - Name(PCIB, Package(){ - }) diff --git a/src/mainboard/lenovo/g505s/acpi/sata.asl b/src/mainboard/lenovo/g505s/acpi/sata.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/sata.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/g505s/acpi/sleep.asl b/src/mainboard/lenovo/g505s/acpi/sleep.asl deleted file mode 100644 index cd714cec87..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/sleep.asl +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*CSSM = 1 - SSEN = 1*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\_SB.SBRI <= 0x13) { - * \_SB.PWDE = 0 - *} - */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 - - UPWS = 0x07 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - USBS = 1 - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/lenovo/g505s/acpi/superio.asl b/src/mainboard/lenovo/g505s/acpi/superio.asl deleted file mode 100644 index 6a6b217e17..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/superio.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* Defines EC bits specific to the mainboard, needed by EC ASL */ -#include "mainboard.h" - -/* ACPI code for EC SuperIO functions */ -#include <ec/compal/ene932/acpi/superio.asl> diff --git a/src/mainboard/lenovo/g505s/acpi/thermal.asl b/src/mainboard/lenovo/g505s/acpi/thermal.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/thermal.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl deleted file mode 100644 index d90fffdd40..0000000000 --- a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/lenovo/g505s/board_info.txt b/src/mainboard/lenovo/g505s/board_info.txt deleted file mode 100644 index c259823965..0000000000 --- a/src/mainboard/lenovo/g505s/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: laptop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Release year: 2013 diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c deleted file mode 100644 index 3bf316e4fd..0000000000 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "mainboard.h" - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> - -/* Include the files that instantiate the configuration definitions. */ -#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> -/* AGESA nonsense: the next two headers depend on heapManager.h */ -#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> -/* These tables are optional and may be used to adjust memory timing settings */ -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - -/* Select the CPU family */ -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE - -/* Build configuration values here */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_SYNC_FLOOD FALSE - -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ - -#define BLDCFG_IOMMU_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE - -/* - * The GPIO control is not well documented in AGESA, but is in the BKDG - * - * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route - * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1 - * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs - * are mostly in Function1, sometimes Function2. - * - * Note that the GpioOut bit does not mean that the GPIO is an output. That bit - * actually controls the output value, so GpioOut means "default to set". - * PullUpB is an inverted logic, so setting this bit means we're actually - * disabling the internal pull-up. The PullDown bit is NOT inverted logic. - * The output driver can be disabled with the GpioOutEnB bit, which is again, - * inverted logic. To make the list more readable, we define a few local macros - * to state what we mean. - */ -#define OUTPUT_HIGH (GpioOut) -#define OUTPUT_LOW (0) -#define INPUT (GpioOutEnB) -#define PULL_UP (0) -#define PULL_DOWN (PullDown | PullUpB) -#define PULL_NONE (PullUpB) - -CONST GPIO_CONTROL lenovo_g505s_gpio[] = { - {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */ - {-1} -}; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (lenovo_g505s_gpio) - -/* - * These definitions could be moved to a common Hudson header, should we decide - * to provide our own, saner SCI mapping function - */ -#define GEVENT_PIN(gpe) ((gpe) + 0x40) -#define SCI_MAP_OHCI_12_0 0x58 -#define SCI_MAP_OHCI_13_0 0x59 -#define SCI_MAP_XHCI_10_0 0x78 -#define SCI_MAP_PWRBTN 0x73 - -CONST SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { - {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, - {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, - {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, - {SCI_MAP_OHCI_12_0, PME_GPE}, - {SCI_MAP_OHCI_13_0, PME_GPE}, - {SCI_MAP_XHCI_10_0, PME_GPE}, - {SCI_MAP_PWRBTN, PME_GPE}, -}; -#define BLDCFG_FCH_SCI_MAP_LIST (lenovo_g505s_sci_map) - -/* - * Process the options... - * This file include MUST occur AFTER the user option selection settings. - * AGESA nonsense: Moving this include up will break AGESA. - */ -#include <PlatformInstall.h> diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout deleted file mode 100644 index 7354972180..0000000000 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ /dev/null @@ -1,36 +0,0 @@ -#***************************************************************************** -# SPDX-License-Identifier: GPL-2.0-only - -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#400 8 r 8 reserved for century byte -408 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/lenovo/g505s/config_seabios b/src/mainboard/lenovo/g505s/config_seabios deleted file mode 100644 index 1959fa35c2..0000000000 --- a/src/mainboard/lenovo/g505s/config_seabios +++ /dev/null @@ -1,7 +0,0 @@ -### -### SeaBIOS custom configuration for Lenovo G505S -### -# CONFIG_MEGASAS is not set -# CONFIG_NVME is not set -# CONFIG_TCGBIOS is not set -# diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb deleted file mode 100644 index 4b4df367b1..0000000000 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ /dev/null @@ -1,69 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 off end - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 off end # - device pci 7.0 off end # - device pci 8.0 off end # NB/SB Link P2P bridge ? - device pci 9.0 off end # - end #chip northbridge/amd/agesa/family15tn - - chip southbridge/amd/agesa/hudson - device pci 10.0 on end # FCH USB XHCI Controller HC0 - device pci 11.0 on end # FCH SATA Controller [AHCI mode] - device pci 12.0 on end # FCH USB OHCI Controller - device pci 12.2 on end # FCH USB EHCI Controller - device pci 13.0 on end # FCH USB OHCI Controller - device pci 13.2 on end # FCH USB EHCI Controller - device pci 14.0 on end # SMBUS - device pci 14.2 on end # FCH Azalia Controller - device pci 14.3 on # FCH LPC Bridge [1022:780e] - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end - end - device pci 14.4 on end # FCH PCI Bridge [1022:780f] - device pci 14.5 off end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family15tn - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl deleted file mode 100644 index c7ab79278e..0000000000 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "mainboard.h" - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_SB) */ - #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - - /* Describe the supported Sleep States for this Southbridge */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ - #include "acpi/sleep.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End Scope(_SB) */ - - Scope(\_SB.PCI0.LIBR) { - #include "acpi/ec.asl" - } - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/lenovo/g505s/ec.c b/src/mainboard/lenovo/g505s/ec.c deleted file mode 100644 index 44eb8cf1c7..0000000000 --- a/src/mainboard/lenovo/g505s/ec.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include "ec.h" -#include <ec/compal/ene932/ec.h> - -/* The keyboard matrix tells the EC how the keyboard is wired internally */ -static void set_keyboard_matrix_us(void) -{ - ec_kbc_write_cmd(0x59); - ec_kbc_write_ib(0xE5); -} - -/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */ -static void enter_apm_mode(void) -{ - ec_kbc_write_cmd(0x59); - ec_kbc_write_ib(0xE9); -} - -void lenovo_g505s_ec_init(void) -{ - set_keyboard_matrix_us(); - - /* - * The EC has a special "blinking Caps Lock LED" mode which it normally - * enters when it believes the OS is not responding. It occasionally - * disables battery charging when in this mode, although other - * functionality is unaffected. Although the EC starts in APM mode by - * default, it only leaves the "blinking Caps Lock LED" mode after - * receiving the following command. - */ - enter_apm_mode(); -} diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h deleted file mode 100644 index 8b17392e76..0000000000 --- a/src/mainboard/lenovo/g505s/ec.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _MAINBOARD_LENOVO_G505S_EC_H -#define _MAINBOARD_LENOVO_G505S_EC_H - -#include "mainboard.h" - -void lenovo_g505s_ec_init(void); - -#endif /* _MAINBOARD_LENOVO_G505S_EC_H */ diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c deleted file mode 100644 index 36caea97de..0000000000 --- a/src/mainboard/lenovo/g505s/irq_tables.c +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/pirq_routing.h> -#include <console/console.h> -#include <commonlib/bsd/helpers.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c deleted file mode 100644 index c1ed48652c..0000000000 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "ec.h" - -#include <acpi/acpi.h> -#include <cpu/x86/smm.h> -#include <device/device.h> -#include <southbridge/amd/common/amd_pci_util.h> - -#include <southbridge/amd/agesa/hudson/smi.h> - -static const u8 mainboard_picr_data[0x54] = { - 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F -}; -static const u8 mainboard_intr_data[0x54] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x11, 0x12, 0x13 -}; - -static void pavilion_cold_boot_init(void) -{ - /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ - hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, SMI_LVL_LOW); - /* EC is not powered off during S3 sleep */ - lenovo_g505s_ec_init(); -} - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -static void mainboard_enable(struct device *dev) -{ - pirq_setup(); - - hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); - global_smi_enable(); - - if (!acpi_is_wakeup_s3()) - pavilion_cold_boot_init(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h deleted file mode 100644 index d4ca524835..0000000000 --- a/src/mainboard/lenovo/g505s/mainboard.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * "The way things are connected" and a few setup options - */ - -#ifndef _MAINBOARD_LENOVO_G505S_MAINBOARD_H -#define _MAINBOARD_LENOVO_G505S_MAINBOARD_H - -/* What is connected to GEVENT pins */ -#define EC_SCI_GEVENT 3 -#define EC_LID_GEVENT 22 -#define EC_SMI_GEVENT 23 -#define PCIE_GEVENT 8 - -/* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but - * we make the distinction between GEVENT pin and SCI. - */ -#define EC_SCI_GPE EC_SCI_GEVENT -#define EC_LID_GPE EC_LID_GEVENT -#define PME_GPE 0x0b -#define PCIE_GPE 0x18 - -/* Enable PS/2 Keyboard and Mouse */ -#define SIO_EC_ENABLE_PS2K - -#endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H */ diff --git a/src/mainboard/lenovo/g505s/smihandler.c b/src/mainboard/lenovo/g505s/smihandler.c deleted file mode 100644 index fa81b280ee..0000000000 --- a/src/mainboard/lenovo/g505s/smihandler.c +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * SMI handler -- mostly takes care of SMIs from the EC - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <ec/compal/ene932/ec.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <southbridge/amd/agesa/hudson/smi.h> - -#include "ec.h" - -#define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10) - -enum sleep_states { - S0 = 0, - S1 = 1, - S3 = 3, - S4 = 4, - S5 = 5, -}; - -enum ec_smi_event { - EC_SMI_EVENT_IDLE = 0x80, - EC_SMI_BATTERY_LOW = 0xb3, -}; - -/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */ -static void ec_enter_apm_mode(void) -{ - ec_kbc_write_cmd(0x59); - ec_kbc_write_ib(0xE9); -} -/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs */ -static void ec_enter_acpi_mode(void) -{ - ec_kbc_write_cmd(0x59); - ec_kbc_write_ib(0xE8); -} - -static uint8_t ec_get_smi_event(void) -{ - ec_kbc_write_cmd(0x56); - return ec_kbc_read_ob(); -} - -static void ec_process_smi(uint8_t src) -{ - /* Reading the SMI source satisfies the EC in terms of responding to - * the event, regardless of whether we take an action or not. - */ - - switch (src) { - case EC_SMI_BATTERY_LOW: - printk(BIOS_DEBUG, "Battery low. Shutting down\n"); - outl(ACPI_PM1_CNT_SLEEP(S5), ACPI_PM1_CNT_BLK); - break; - default: - printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src); - } -} - -static void handle_ec_smi(void) -{ - uint8_t src; - - while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE) - ec_process_smi(src); -} - -static void handle_lid_smi(void) -{ - /* Only triggered in non-ACPI mode on lid close. */ - outl(ACPI_PM1_CNT_SLEEP(S4), ACPI_PM1_CNT_BLK); -} - -int mainboard_smi_apmc(uint8_t data) -{ - switch (data) { - case ACPI_SMI_CMD_ENABLE: - printk(BIOS_DEBUG, "Enable ACPI mode\n"); - ec_enter_acpi_mode(); - hudson_disable_gevent_smi(EC_LID_GEVENT); - break; - case ACPI_SMI_CMD_DISABLE: - printk(BIOS_DEBUG, "Disable ACPI mode\n"); - ec_enter_apm_mode(); - hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, - SMI_LVL_LOW); - break; - default: - printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data); - } - return 0; -} - -void mainboard_smi_gpi(uint32_t gpi_sts) -{ - if (gpi_sts & (1 << EC_SMI_GEVENT)) - handle_ec_smi(); - if (gpi_sts & (1 << EC_LID_GEVENT)) - handle_lid_smi(); -} diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c deleted file mode 100644 index ca34dcdc2b..0000000000 --- a/src/mainboard/msi/ms7721/BiosCallOuts.c +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> - -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * MSI MS-7721 board ALC887-VD Verb Table - * - * Copied from `/sys/class/sound/hwC1D3/init_pin_configs` when running - * the vendor BIOS. - */ -const CODEC_ENTRY ms7721_alc887_VerbTbl[] = { -{0x11, 0x411111f0}, -{0x12, 0x411111f0}, -{0x14, 0x01014410}, -{0x15, 0x01011412}, -{0x16, 0x01016411}, -{0x17, 0x01012414}, -{0x18, 0x01a19c30}, -{0x19, 0x02a19c40}, -{0x1a, 0x0181343f}, -{0x1b, 0x02214c20}, -{0x1c, 0x411111f0}, -{0x1d, 0x4007f603}, -{0x1e, 0x411111f0}, -{0x1f, 0x411111f0} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0887, (CODEC_ENTRY*)&ms7721_alc887_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - /* Fan Control */ - FchParams_env->Imc.ImcEnable = FALSE; - FchParams_env->Hwm.HwMonitorEnable = FALSE; - FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ -} diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig deleted file mode 100644 index be616379f2..0000000000 --- a/src/mainboard/msi/ms7721/Kconfig +++ /dev/null @@ -1,59 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_MSI_MS7721 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - select SOUTHBRIDGE_AMD_AGESA_HUDSON - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_ACPI_TABLES - select SUPERIO_FINTEK_F71869AD - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -config MAINBOARD_DIR - default "msi/ms7721" - -config MAINBOARD_PART_NUMBER - default "MS-7721" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config HUDSON_XHCI_FWM - bool - default n - -config HUDSON_IMC_FWM - bool - default n - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1002,990e" - -config HUDSON_LEGACY_FREE - bool - default n - -config POST_IO - bool - default n - -endif # BOARD_MSI_MS7721 diff --git a/src/mainboard/msi/ms7721/Kconfig.name b/src/mainboard/msi/ms7721/Kconfig.name deleted file mode 100644 index bce5b99d43..0000000000 --- a/src/mainboard/msi/ms7721/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_MSI_MS7721 - bool "MS-7721 (FM2-A75MA-E35)" diff --git a/src/mainboard/msi/ms7721/Makefile.inc b/src/mainboard/msi/ms7721/Makefile.inc deleted file mode 100644 index 549801d78f..0000000000 --- a/src/mainboard/msi/ms7721/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c deleted file mode 100644 index ae7a945921..0000000000 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ /dev/null @@ -1,181 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <Porting.h> -#include <AGESA.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - -/* - * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) - * - * Lane Id - * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 - * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 - * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 - * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 - * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 - * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 - * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 - * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 - * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI - * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI - * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI - * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI - * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI - * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI - * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI - * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI - * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI - * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI - * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI - * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI - * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI - * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI - * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI - * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI - * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) - * 25 DP0_TX[P,N]1 - * 26 DP0_TX[P,N]2 - * 27 DP0_TX[P,N]3 - * 28 DP1_TX[P,N]0 - * 29 DP1_TX[P,N]1 - * 30 DP1_TX[P,N]2 - * 31 DP1_TX[P,N]3 - * 32 DP2_TX[P,N]0 - * 33 DP2_TX[P,N]1 - * 34 DP2_TX[P,N]2 - * 35 DP2_TX[P,N]3 - * 36 DP2_TX[P,N]4 - * 37 DP2_TX[P,N]5 - * 38 DP2_TX[P,N]6 - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2, x16 slot */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - // DP0 to HDMI0/DP - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) - }, - // DP1 to FCH - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - // DP2 to HDMI1/DP - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), -/* - TODO: is this OK for DDR3 socket FM2? - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - */ - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/msi/ms7721/acpi/cpstate.asl b/src/mainboard/msi/ms7721/acpi/cpstate.asl deleted file mode 100644 index 494fc73201..0000000000 --- a/src/mainboard/msi/ms7721/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package() - { - 0x00000D48, - 0x00011170, - 0x00000004, - 0x00000004, - 0x00000000, - 0x00000000 - }, - - Package() - { - 0x00000AF0, - 0x0000C544, - 0x00000004, - 0x00000004, - 0x00000001, - 0x00000001 - }, - - Package() - { - 0x000009C4, - 0x0000B3B0, - 0x00000004, - 0x00000004, - 0x00000002, - 0x00000002 - }, - - Package() - { - 0x00000898, - 0x0000ABE0, - 0x00000004, - 0x00000004, - 0x00000003, - 0x00000003 - }, - - Package() - { - 0x00000708, - 0x0000A410, - 0x00000004, - 0x00000004, - 0x00000004, - 0x00000004 - }, - - Package() - { - 0x00000578, - 0x00006F54, - 0x00000004, - 0x00000004, - 0x00000005, - 0x00000005 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/msi/ms7721/acpi/gpe.asl b/src/mainboard/msi/ms7721/acpi/gpe.asl deleted file mode 100644 index 30d10ce741..0000000000 --- a/src/mainboard/msi/ms7721/acpi/gpe.asl +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/msi/ms7721/acpi/routing.asl b/src/mainboard/msi/ms7721/acpi/routing.asl deleted file mode 100644 index 8aa35a733d..0000000000 --- a/src/mainboard/msi/ms7721/acpi/routing.asl +++ /dev/null @@ -1,244 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - - /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* SB devices */ - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - - /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 17 }, - Package(){0x0015FFFF, 1, 0, 18 }, - Package(){0x0015FFFF, 2, 0, 19 }, - Package(){0x0015FFFF, 3, 0, 16 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - /* black slot */ - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PBR0, Package(){ - /* PCIx1 on SB */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(ABR0, Package(){ - /* PCIx1 on SB */ - Package(){0x0000FFFF, 0, 0, 0x10 }, - Package(){0x0000FFFF, 1, 0, 0x11 }, - Package(){0x0000FFFF, 2, 0, 0x12 }, - Package(){0x0000FFFF, 3, 0, 0x13 }, - }) - - Name(PBR1, Package(){ - /* Onboard network */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(ABR1, Package(){ - /* Onboard network */ - Package(){0x0000FFFF, 0, 0, 0x11 }, - Package(){0x0000FFFF, 1, 0, 0x12 }, - Package(){0x0000FFFF, 2, 0, 0x13 }, - Package(){0x0000FFFF, 3, 0, 0x10 }, - }) - - /* SB PCI Bridge */ - Name(PCIB, Package(){ - /* PCI slots: slot 0 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - }) diff --git a/src/mainboard/msi/ms7721/acpi/sata.asl b/src/mainboard/msi/ms7721/acpi/sata.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/msi/ms7721/acpi/sata.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/msi/ms7721/acpi/sleep.asl b/src/mainboard/msi/ms7721/acpi/sleep.asl deleted file mode 100644 index 07f6419b64..0000000000 --- a/src/mainboard/msi/ms7721/acpi/sleep.asl +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*CSSM = 1 - SSEN = 1*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\_SB.SBRI <= 0x13) { - * \_SB.PWDE = 0 - *} - */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 - - UPWS = 0x07 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/msi/ms7721/acpi/superio.asl b/src/mainboard/msi/ms7721/acpi/superio.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/msi/ms7721/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/msi/ms7721/acpi/thermal.asl b/src/mainboard/msi/ms7721/acpi/thermal.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/msi/ms7721/acpi/thermal.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/msi/ms7721/board_info.txt b/src/mainboard/msi/ms7721/board_info.txt deleted file mode 100644 index 6792e8e49b..0000000000 --- a/src/mainboard/msi/ms7721/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: https://www.msi.com/Motherboard/FM2-A75MA-E35.html -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Release year: 2012 diff --git a/src/mainboard/msi/ms7721/bootblock.c b/src/mainboard/msi/ms7721/bootblock.c deleted file mode 100644 index 0de0c58f3d..0000000000 --- a/src/mainboard/msi/ms7721/bootblock.c +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pnp_def.h> -#include <device/pnp_ops.h> -#include <device/pnp_type.h> -#include <stdint.h> -#include <amdblocks/acpimmio.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f71869ad/f71869ad.h> - -/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ -#define SUPERIO_ADDRESS 0x4e - -#define SERIAL_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_SP1) -#define GPIO_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_GPIO) - -/* GPIO configuration */ -static void gpio_init(pnp_devfn_t dev) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, PNP_IDX_IO0, 0x0a); //Base addr high - pnp_write_config(dev, 0x61, 0x00); //Base addr low - pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable - pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data - pnp_write_config(dev, 0xe3, 0x04); //GPIO1 drive enable - pnp_write_config(dev, 0xe4, 0x00); //GPIO1 PME enable - pnp_write_config(dev, 0xe5, 0x00); //GPIO1 input detect select - pnp_write_config(dev, 0xe6, 0x40); //GPIO1 event status - pnp_write_config(dev, 0xd0, 0x00); //GPIO2 output enable - pnp_write_config(dev, 0xd1, 0xff); //GPIO2 output data - pnp_write_config(dev, 0xd3, 0x00); //GPIO2 drive enable - pnp_write_config(dev, 0xc0, 0x00); //GPIO3 output enable - pnp_write_config(dev, 0xc1, 0xff); //GPIO3 output data - pnp_write_config(dev, 0xb0, 0x04); //GPIO4 output enable - pnp_write_config(dev, 0xb1, 0x04); //GPIO4 output data - pnp_write_config(dev, 0xb3, 0x04); //GPIO4 drive enable - pnp_write_config(dev, 0xb4, 0x00); //GPIO4 PME enable - pnp_write_config(dev, 0xb5, 0x00); //GPIO4 input detect select - pnp_write_config(dev, 0xb6, 0x00); //GPIO4 event status - pnp_write_config(dev, 0xa0, 0x00); //GPIO5 output enable - pnp_write_config(dev, 0xa1, 0x1f); //GPIO5 output data - pnp_write_config(dev, 0xa3, 0x00); //GPIO5 drive enable - pnp_write_config(dev, 0xa4, 0x00); //GPIO5 PME enable - pnp_write_config(dev, 0xa5, 0xff); //GPIO5 input detect select - pnp_write_config(dev, 0xa6, 0xe0); //GPIO5 event status - pnp_write_config(dev, 0x90, 0x00); //GPIO6 output enable - pnp_write_config(dev, 0x91, 0xff); //GPIO6 output data - pnp_write_config(dev, 0x93, 0x00); //GPIO6 drive enable - pnp_write_config(dev, 0x80, 0x00); //GPIO7 output enable - pnp_write_config(dev, 0x81, 0xff); //GPIO7 output data - pnp_write_config(dev, 0x83, 0x00); //GPIO7 drive enable - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} - -static void sbxxx_enable_48mhzout(void) -{ - /* most likely programming to 48MHz out signal */ - u32 reg32; - reg32 = misc_read32(0x28); - reg32 &= 0xffc7ffff; - reg32 |= 0x00100000; - misc_write32(0x28, reg32); - - reg32 = misc_read32(0x40); - reg32 &= ~0x80u; - misc_write32(0x40, reg32); -} - -void bootblock_mainboard_early_init(void) -{ - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Initialize GPIO registers */ - gpio_init(GPIO_DEV); - - /* Enable serial console */ - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c deleted file mode 100644 index dd5f8940d9..0000000000 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> - -/* Include the files that instantiate the configuration definitions. */ -#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> -/* AGESA nonsense: the next two headers depend on heapManager.h */ -#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> -/* These tables are optional and may be used to adjust memory timing settings */ -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - -/* Select the CPU family */ -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FM2_SOCKET_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE - -/* Build configuration values here */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY -#define BLDCFG_ENABLE_ECC_FEATURE FALSE -#define BLDCFG_ECC_SYNC_FLOOD FALSE - -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ - -#define BLDCFG_IOMMU_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE - -/* Customized OEM build configurations for FCH component */ -#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 -#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE -#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE - -CONST GPIO_CONTROL ms7721_m_gpio[] = { - {-1} -}; - -#define BLDCFG_FCH_GPIO_CONTROL_LIST (ms7721_m_gpio) - -/* - * Process the options... - * This file include MUST occur AFTER the user option selection settings. - * AGESA nonsense: Moving this include up will break AGESA. - */ -#include <PlatformInstall.h> diff --git a/src/mainboard/msi/ms7721/cmos.layout b/src/mainboard/msi/ms7721/cmos.layout deleted file mode 100644 index a11e1dd0e6..0000000000 --- a/src/mainboard/msi/ms7721/cmos.layout +++ /dev/null @@ -1,35 +0,0 @@ -#***************************************************************************** -# SPDX-License-Identifier: GPL-2.0-only - -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb deleted file mode 100644 index 6d2c1a486a..0000000000 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ /dev/null @@ -1,156 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x990e - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe x16 - device pci 3.0 off end # - - device pci 4.0 on end # PCIE Realtek LAN - device pci 5.0 on end # PCIE x1 (1) - device pci 6.0 on end # PCIE x1 (2) - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn - - chip southbridge/amd/agesa/hudson - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB OHCI - device pci 12.2 on end # USB EHCI - device pci 13.0 on end # USB OHCI - device pci 13.2 on end # USB EHCI - device pci 14.0 on end # SMBUS - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # Azalia (Audio) - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71869ad - register "multi_function_register_1" = "0x01" - register "multi_function_register_2" = "0x0f" - register "multi_function_register_3" = "0x2f" - register "multi_function_register_4" = "0x04" - register "multi_function_register_5" = "0x3e" - - # HWM configuration registers - register "hwm_smbus_address" = "0x98" - register "hwm_smbus_control_reg" = "0x02" - register "hwm_fan_type_sel_reg" = "0x00" - register "hwm_fan1_temp_adj_rate_reg" = "0x33" - register "hwm_fan_mode_sel_reg" = "0x07" - register "hwm_fan1_idx_rpm_mode" = "0x0e" - register "hwm_fan1_seg1_speed_count" = "0xff" - register "hwm_fan1_seg2_speed_count" = "0x0e" - register "hwm_fan1_seg3_speed_count" = "0x07" - register "hwm_fan1_temp_map_sel" = "0x8c" - register "hwm_temp_sensor_type" = "0x08" - - device pnp 4e.00 off end - device pnp 4e.01 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.02 off # COM2 (Level converter not populated, but may be usable?) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.03 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 3 - irq 0xf0 = 0x44 # PRT Mode Select Register - end - device pnp 4e.04 on # Hardware Monitor - io 0x60 = 0x225 # Fintek datasheet says 0x295. - irq 0x70 = 0 - end - device pnp 4e.05 on # KBC - io 0x60 = 0x060 - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - end - device pnp 4e.06 on # GPIO - # ! GPIO config is disabled because the code in romstage.c - # ! has already taken care of it - #io 0x60 = 0xa00 - #irq 0xe0 = 0x04 # GPIO1 output - #irq 0xe1 = 0xff # GPIO1 output data - #irq 0xe3 = 0x04 # GPIO1 drive enable - #irq 0xe4 = 0x00 # GPIO1 PME enable - #irq 0xe5 = 0x00 # GPIO1 input detect select - #irq 0xe6 = 0x40 # GPIO1 event status - - #irq 0xd0 = 0x00 # GPIO2 output - #irq 0xd1 = 0xff # GPIO2 output data - #irq 0xd3 = 0x00 # GPIO2 drive enable - - #irq 0xc0 = 0x00 # GPIO3 output - #irq 0xc1 = 0xff # GPIO3 output data - - #irq 0xb0 = 0x04 # GPIO4 output - #irq 0xb1 = 0x04 # GPIO4 output data - #irq 0xb3 = 0x04 # GPIO4 drive enable - #irq 0xb4 = 0x00 # GPIO4 PME enable - #irq 0xb5 = 0x00 # GPIO4 input detect select - #irq 0xb6 = 0x00 # GPIO4 event status - - #irq 0xa0 = 0x00 # GPIO5 output - #irq 0xa1 = 0x1f # GPIO5 output data - #irq 0xa3 = 0x00 # GPIO5 drive enable - #irq 0xa4 = 0x00 # GPIO5 PME enable - #irq 0xa5 = 0xff # GPIO5 input detect select - #irq 0xa6 = 0xe0 # GPIO5 event status - - #irq 0x90 = 0x00 # GPIO6 output - #irq 0x91 = 0xff # GPIO6 output data - #irq 0x93 = 0x00 # GPIO6 drive enable - - #irq 0x80 = 0x00 # GPIO7 output - #irq 0x81 = 0xff # GPIO7 output data - #irq 0x83 = 0x00 # GPIO7 drive enable - end - - device pnp 4e.07 on end # WDT - device pnp 4e.08 off end # CIR - device pnp 4e.0a on end # PME - end # f71869ad - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 (PCI slot on board) - device pci 14.5 on end # USB OHCI - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # unused - device pci 15.1 off end # unused - device pci 15.2 off end # unused - device pci 15.3 off end # unused - - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family15tn - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl deleted file mode 100644 index 3e67f63776..0000000000 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - #include <arch/x86/acpi/debug.asl> /* Include global debug methods if needed */ - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_SB) */ - #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - - /* Describe the supported Sleep States for this Southbridge */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ - #include "acpi/sleep.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - /* Describe USB for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/usb.asl> - - } /* End Scope(_SB) */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/msi/ms7721/irq_tables.c b/src/mainboard/msi/ms7721/irq_tables.c deleted file mode 100644 index a0997f88c4..0000000000 --- a/src/mainboard/msi/ms7721/irq_tables.c +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/pirq_routing.h> -#include <console/console.h> -#include <commonlib/bsd/helpers.h> -#include <device/pci_def.h> -#include <stdint.h> -#include <string.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c deleted file mode 100644 index 37bce31c80..0000000000 --- a/src/mainboard/msi/ms7721/mainboard.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <device/device.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static const u8 mainboard_picr_data[] = { - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F -}; -static const u8 mainboard_intr_data[0x54] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x11, 0x12, 0x13 -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/************************************************* - * enable the dedicated function in thatcher board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - msr_t msr; - - pirq_setup(); - - msr = rdmsr(LS_CFG_MSR); - msr.lo &= ~(1 << 28); - wrmsr(LS_CFG_MSR, msr); - - msr = rdmsr(DC_CFG_MSR); - msr.lo &= ~(1 << 4); - msr.lo &= ~(1 << 13); - wrmsr(DC_CFG_MSR, msr); - - msr = rdmsr(BU_CFG_MSR); - msr.lo &= ~(1 << 23); - wrmsr(BU_CFG_MSR, msr); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c deleted file mode 100644 index 6f96ed8f0f..0000000000 --- a/src/mainboard/msi/ms7721/romstage.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - post_code(0x30); -} |