mb/asrock/z97_extreme6: Add new mainboard

That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.

This board has two socketed DIP-8 SPI flash chips and a physical switch
to choose which one should the system boot from. As long as one of them
contains a bootable firmware image, it is possible to reflash the other
chip using the internal programmer by flipping the switch after booting
to OS. Even if one somehow manages to flash unbootable firmware to both
chips, they are socketed: one can carefully remove them from the socket
and reflash them externally, which is a relatively safe procedure (when
compared to in-circuit flashing, especially if the board isn't designed
to safely be flashed in-circuit). In short, the board is hard to brick.

Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH
found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs
so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe
it's something about RcvEn, but it's unlikely it can easily be fixed.

Working:
 - All four DIMM slots
 - Broadwell MRC.bin for raminit purposes
 - Serial port to emit spam
 - POST code display
 - S3 suspend/resume
 - All rear USB 3.0 ports
 - Internal USB 2.0 port
 - Audio output (green jack)
 - Integrated graphics (libgfxinit)
 - HDMI
 - VBT
 - Intel GbE (I218-V PHY and PCH MAC)
 - Realtek RTL8111E GbE
 - At least one SATA port
 - M2_1 slot (Gen3 x4, bifurcated from CPU)
 - Flashing internally with flashrom
 - SeaBIOS (current version) to boot Arch Linux
 - NCT6791D Super I/O software-based fan control
   tested using `sensors` and `pwmconfig`, all 6
   fan tachometers and 5 PWM outputs work fine.

Untested for now (i.e. should work, will eventually test):
 - DVI-I, DisplayPort
 - EHCI debug
 - Front USB 2.0 and 3.0 ports
 - The other audio jacks (as well as SPDIF)
 - The other PCIe and M.2 ports
 - Non-Linux OSes
 - PS/2 combo port (can only test with a keyboard)

Untestable (i.e. cannot test due to unavailable hardware):
 - Thunderbolt AIC (Add-In Card) support

Not working:
 - Broadwell CPUs, they require more magic to work (working on it).
 - Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were
   not tested. It seems that the problem is with the controllers.
 - Super I/O automatic fan control: not yet implemented in coreboot.
   To control fans, use software fan control methods in the meantime.
 - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor,
   connected to the board's HDMI output says "Unsupported resolution"
   after libgfxinit configured the iGPU outputs in linear framebuffer
   mode. HDMI output works fine after Linux's i915 driver takes over.
   Not sure if it's specific to the monitor: the HDMI cable is beaten
   up, and it is hard to replace (need to relocate the logic board so
   that the ports are accessible).

Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 126 insertions, 0 deletions

diff --git a/src/mainboard/asrock/z97_extreme6/bootblock.c b/src/mainboard/asrock/z97_extreme6/bootblock.c
new file mode 100644
index 0000000000..318cc034f2
--- /dev/null
+++ b/src/mainboard/asrock/z97_extreme6/bootblock.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pnp_ops.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6791d/nct6791d.h>
+
+#define GLOBAL_DEV	PNP_DEV(0x2e, 0)
+#define SERIAL_DEV	PNP_DEV(0x2e, NCT6791D_SP1)
+#define ACPI_DEV	PNP_DEV(0x2e, NCT6791D_ACPI)
+#define GPIO_PP_OD_DEV	PNP_DEV(0x2e, NCT6791D_GPIO_PP_OD)
+
+/*
+ * Asrock Z97 Extreme6 Super I/O GPIOs
+ *
+ * +------+-----+---------------------------+
+ * | GPIO | Pin | Description               |
+ * +------+-----+---------------------------+
+ * | GP00 | 121 | N/C                       |
+ * | GP01 | 122 | CHA_FAN2 PWM output       |
+ * | GP02 | 123 | CHA_FAN3 PWM output       |
+ * | GP03 |   2 | N/C                       |
+ * | GP04 |   3 | CHA_FAN3 tach input       |
+ * | GP05 |   4 | CHA_FAN2 tach input       |
+ * | GP06 |   5 | PWR_FAN  tach input       |
+ * | GP07 |   6 | N/C            (SE_IFDET) |
+ * +------+-----+---------------------------+
+ * | GP10 |  14 | HDD Saver power switch    |
+ * | GP11 |  13 | Assert HDA_SDO (SIO_GP11) |
+ * | GP12 |  12 | CPU_FAN2 FON#             |
+ * | GP13 |  11 | SATA_SEL (for eSATA)      |
+ * | GP14 |  10 | N/C                       |
+ * | GP15 |   9 | N/C          (UARTP80_EN) |
+ * | GP16 |   8 | OTP for VCORE (OTE_GATE1) |
+ * | GP17 |   7 | LED_EN#                   |
+ * +------+-----+---------------------------+
+ * | GP20 |  59 | KDAT                      |
+ * | GP21 |  58 | KCLK                      |
+ * | GP22 |  57 | MDAT                      |
+ * | GP23 |  56 | MCLK                      |
+ * | GP24 |  95 | SE_DEVSLP (SATA Express)  |
+ * | GP25 |  96 | N/C            (SIO_GP25) |
+ * | GP26 |  53 | N/C                       |
+ * | GP27 |  98 | M2_2_SE_IFDET             |
+ * +------+-----+---------------------------+
+ * | GP30 |  83 | N/C           (RESETCON#) |
+ * | GP31 |  76 | BIOS_A (or SML1DAT)       |
+ * | GP32 |  75 | BIOS_B (or SML1CLK)       |
+ * | GP33 |  71 | 3VSBSW#                   |
+ * | GP34 |  55 | VCORE_OFFSET#             |
+ * | GP35 |  54 | N/C                       |
+ * | GP36 |  53 | N/C                       |
+ * | GP37 |   7 | LED_EN#                   |
+ * +------+-----+---------------------------+
+ * | GP40 |  62 | N/C             (TEST_EN) |
+ * | GP41 |  52 | N/C                       |
+ * | GP42 |  51 | WLAN1_ON/OFF#             |
+ * | GP43 |  41 | Port 80 display - DGL_0#  |
+ * | GP44 |  40 | PWR_LED gate              |
+ * | GP45 |  39 | HDD_LED gate              |
+ * | GP46 |  38 | CHA_FAN3 FON#             |
+ * | GP47 |  37 | CHA_FAN2 FON#             |
+ * +------+-----+---------------------------+
+ * | GP50 |  93 | N/C            (SUSWARN#) |
+ * | GP51 |  92 | CPU_FAN2 tach input       |
+ * | GP52 |  91 | N/C             (SUSACK#) |
+ * | GP53 |  90 | SUSWARN_5VDUAL            |
+ * | GP54 |  89 | SLP_SUS#                  |
+ * | GP55 |  88 | SLP_SUS_FET               |
+ * | GP56 |  87 | PEG12V_DET (Molex conn)   |
+ * | GP57 |  86 | PCIE4_SEL (PCIE3 / mPCIe) |
+ * +------+-----+---------------------------+
+ * | GP70 |  69 | N/C              (DSW_EN) |
+ * | GP71 |  68 | N/C                       |
+ * | GP72 |  67 | N/C                       |
+ * | GP73 |  66 | M.2 / SATA Express select |
+ * | GP74 |  79 | RESET# of long PCIe ports |
+ * | GP75 |  78 | RESET# for on-board chips |
+ * | GP76 |  77 | RESET# SATA Express / M.2 |
+ * | GP77 |  86 | HDD_LED gate              |
+ * +------+-----+---------------------------+
+ *
+ * HWM voltage inputs
+ *
+ * +------+-----+---------------------------+
+ * | Name | Pin | Voltage (resistor values) |
+ * +------+-----+---------------------------+
+ * | VIN0 | 104 | +12V         (110K / 10K) |
+ * | VIN1 | 105 | +5V           (20K / 10K) |
+ * | VIN2 | 106 | CPU_VRING                 |
+ * | VIN3 | 107 | CPU_VSA                   |
+ * | VIN4 | 111 | CPU_VCORE0                |
+ * | VIN5 | 114 | CPU_VGFX                  |
+ * | VIN6 | 115 | V_VCCIOA_LOAD             |
+ * | VIN7 | 116 | N/C                       |
+ * | VIN8 | 103 | CPU_VIO                   |
+ * +------+-----+---------------------------+
+ */
+
+void mainboard_config_superio(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin mux states */
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0xe6);
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x10);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0xfc);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x40);
+	pnp_write_config(GLOBAL_DEV, 0x2b, 0x20);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+	pnp_write_config(GLOBAL_DEV, 0x2d, 0x02);
+
+	/* Select push-pull vs. open-drain output */
+	pnp_set_logical_device(GPIO_PP_OD_DEV);
+	pnp_write_config(GPIO_PP_OD_DEV, 0xe0, 0xfe);
+	pnp_write_config(GPIO_PP_OD_DEV, 0xe2, 0x79);
+	pnp_write_config(GPIO_PP_OD_DEV, 0xe6, 0x6f);
+
+	/* Power RAM in S3 */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}