mb/asrock: Add ASRock H77 Pro4-M mainboard

This adds a new port for the ASRock H77 Pro4-M motherboard. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.

The port was initially done with autoport. It is quite similar to the
ASRock B75 Pro3-M which is already supported by coreboot.

Working:
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
- Native RAM initialization with four DIMMs of two different types
- PS/2 combined port (mouse or keyboard)
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
- PCIe graphics in the PEG slot
- All three additional PCIe slots
- All rear and internal USB2 ports
- All rear and internal USB3 ports with reasonable transfer rates
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
- Rear eSATA connector (multiplexed with one ASM1061 port)
- Console output on the serial port of the Super I/O
- SeaBIOS 1.15.0 to boot slackware64
- SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS)
- Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`)
- External flashing with flashrom-1.2 and a Raspberry Pi 1
- S3 suspend/resume from either Linux or Windows 10

Not working:
- Booting from the two SATA ports provided by the ASM1061
- Automatic fan control with the NCT6776D Super I/O

Untested:
- VBT (it is included, though)
- Infrared header

Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 97 insertions, 0 deletions

diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c
new file mode 100644
index 0000000000..48024cba5c
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/early_init.c
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <option.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define GLOBAL_DEV   PNP_DEV(0x2e, 0)
+#define SERIAL_DEV   PNP_DEV(0x2e, NCT6776_SP1)
+#define GPIO6789_DEV PNP_DEV(0x2e, NCT6776_GPIO6789_V)
+
+/* As defined in cmos.layout */
+enum cpu_fan_tach_src {
+	CPU_FAN_HEADER_NONE,
+	CPU_FAN_HEADER_1,
+	CPU_FAN_HEADER_2,
+	CPU_FAN_HEADER_BOTH
+};
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 1, 1 },
+	{ 1, 1, 1 },
+	{ 1, 1, 2 },
+	{ 1, 1, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 1, 5 },
+	{ 1, 1, 5 },
+	{ 1, 0, 6 },
+};
+
+/*
+ * The tachometer signal that goes to CPUFANIN of the Super I/O is set via
+ * GPIOs.
+ *
+ * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected.
+ * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected.
+ * When both are '0' and both fans are connected, wrong readings will
+ * be reported.
+ */
+static u8 get_cpufanin_gpio_config(void)
+{
+	switch (get_uint_option("cpu_fan_tach_src", CPU_FAN_HEADER_1)) {
+	case CPU_FAN_HEADER_NONE:
+		return 0xff;
+	case CPU_FAN_HEADER_1:
+	default:
+		return 0x7f;
+	case CPU_FAN_HEADER_2:
+		return 0xbf;
+	case CPU_FAN_HEADER_BOTH:
+		return 0x3f;
+	}
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Configure Super I/O pins */
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0x68);
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x80);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0x5c);
+	pnp_write_config(GLOBAL_DEV, 0x27, 0xc0);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x62);
+	pnp_write_config(GLOBAL_DEV, 0x2b, 0x08);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
+
+	/* GP77 and GP76 are outputs. They set the tachometer input on CPUFANIN. */
+	pnp_set_logical_device(GPIO6789_DEV);
+	pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f);
+	pnp_write_config(GPIO6789_DEV, 0xe1, get_cpufanin_gpio_config());
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	/* Enable UART */
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}