mb/asrock: Add ASRock H77 Pro4-M mainboard

This adds a new port for the ASRock H77 Pro4-M motherboard. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.

The port was initially done with autoport. It is quite similar to the
ASRock B75 Pro3-M which is already supported by coreboot.

Working:
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
- Native RAM initialization with four DIMMs of two different types
- PS/2 combined port (mouse or keyboard)
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
- PCIe graphics in the PEG slot
- All three additional PCIe slots
- All rear and internal USB2 ports
- All rear and internal USB3 ports with reasonable transfer rates
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
- Rear eSATA connector (multiplexed with one ASM1061 port)
- Console output on the serial port of the Super I/O
- SeaBIOS 1.15.0 to boot slackware64
- SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS)
- Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`)
- External flashing with flashrom-1.2 and a Raspberry Pi 1
- S3 suspend/resume from either Linux or Windows 10

Not working:
- Booting from the two SATA ports provided by the ASM1061
- Automatic fan control with the NCT6776D Super I/O

Untested:
- VBT (it is included, though)
- Infrared header

Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

18 files changed, 826 insertions, 0 deletions

diff --git a/Documentation/mainboard/asrock/h77pro4-m.md b/Documentation/mainboard/asrock/h77pro4-m.md
new file mode 100644
index 0000000000..45c603d7a3
--- /dev/null
+++ b/Documentation/mainboard/asrock/h77pro4-m.md
@@ -0,0 +1,174 @@
+# ASRock H77 Pro4-M
+
+The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy
+Bridge and Ivy Bridge CPUs.
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | Intel H77 (bd82x6x)                              |
++------------------+--------------------------------------------------+
+| CPU socket       | LGA 1155                                         |
++------------------+--------------------------------------------------+
+| RAM              | 4 x DDR3-1600                                    |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6776                                  |
++------------------+--------------------------------------------------+
+| Audio            | Realtek ALC892                                   |
++------------------+--------------------------------------------------+
+| Network          | Realtek RTL8111E                                 |
++------------------+--------------------------------------------------+
+| Serial           | Internal header (RS-232)                         |
++------------------+--------------------------------------------------+
+```
+
+## Status
+
+Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
+(linux-4.19.50).
+
+### Working
+
+- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
+- Native RAM initialization with four DIMMs
+- PS/2 combined port (mouse or keyboard)
+- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
+- PCIe graphics in the PEG slot
+- All three additional PCIe slots
+- All rear and internal USB2 ports
+- All rear and internal USB3 ports
+- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
+- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
+- Rear eSATA connector (multiplexed with one ASM1061 port)
+- Gigabit Ethernet
+- Console output on the serial port
+- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via
+extlinux
+- Internal flashing with flashrom-1.2, see
+[Internal Programming](#internal-programming)
+- External flashing with flashrom-1.2 and a Raspberry Pi 1
+- S3 suspend/resume from either Linux or Windows 10
+- Poweroff
+
+### Not working
+
+- Booting from the two SATA ports provided by the ASM1061
+- Automatic fan control with the NCT6776D Super I/O
+
+### Untested
+
+- EHCI debug
+- S/PDIF audio
+- Other audio jacks than the green one, and the front panel header
+- Parallel port
+- Infrared/CIR
+- Wakeup from anything but the power button
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | yes        |
++---------------------+------------+
+| Model               | W25Q64.V   |
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| Package             | DIP-8      |
++---------------------+------------+
+| Write protection    | no         |
++---------------------+------------+
+| Dual BIOS feature   | no         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+The flash is divided into the following regions, as obtained with
+`ifdtool -f rom.layout backup.rom`:
+```
+00000000:00000fff fd
+00200000:007fffff bios
+00001000:001fffff me
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using flashrom. By default, only
+the BIOS region of the flash is writable. If you wish to change any
+other region (Management Engine or flash descriptor), then an external
+programmer is required.
+
+The following command may be used to flash coreboot:
+
+```
+$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
+```
+
+The use of `--noverify-all` is required since the Management Engine
+region is not readable even by the host.
+
+```eval_rst
+In addition to the information here, please see the
+:doc:`../../flash_tutorial/index`.
+```
+
+## Hardware monitoring and fan control
+
+There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share
+a single fan tachometer input on the Super I/O while some dedicated logic
+selects which one is allowed to reach it. Two GPIO pins on the Super I/O are
+used to control that logic. The firmware has to set them; coreboot selects
+CPU_FAN1 by default, but the user can change that setting if it was built with
+CONFIG_USE_OPTION_TABLE:
+
+```
+$ sudo nvramtool -e cpu_fan_header
+[..]
+$ sudo nvramtool -w cpu_fan_header=CPU_FAN2
+$ sudo nvramtool -w cpu_fan_header=None
+$ sudo nvramtool -w cpu_fan_header=Both
+```
+
+The setting will take effect after a reboot. Selecting and connecting both fan
+headers is possible but the Super I/O will report wrong fan speeds.
+
+Currently there is no automatic, OS-independent fan control, but a software
+like `fancontrol` from the lm-sensors package can be used instead.
+
+## Serial port header
+
+Serial port 1, provided by the Super I/O, is exposed on a pin header. The
+RS-232 signals are assigned to the header so that its pin numbers map directly
+to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
+work, check if your bracket expects a different assignment. Also don't try to
+connect it directly to a device that operates at TTL levels - it would need a
+level converter like a MAX232.
+
+Here is a top view of the serial port header found on this board:
+
+                 +---+---+
+             N/C |   | 9 | RI  -> pin 9
+                 +---+---+
+    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
+                 +---+---+
+    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
+                 +---+---+
+    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
+                 +---+---+
+    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
+                 +---+---+
+
+## eSATA
+
+The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share
+the same controller port on the ASM1061. Attaching an eSATA drive causes a
+multiplexer chip to disconnect the internal port from the SATA controller and
+connect the eSATA port instead. This can be seen on GP23 of the Super I/O
+GPIOs: it is '0' when something is connected to the eSATA port and '1'
+otherwise.
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 0d5ec5f542..fc602de1a9 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -11,6 +11,7 @@ This section contains documentation about coreboot on specific mainboards.
 
 ## ASRock
 
+- [H77 Pro4-M](asrock/h77pro4-m.md)
 - [H81M-HDS](asrock/h81m-hds.md)
 - [H110M-DVS](asrock/h110m-dvs.md)
 
diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig b/src/mainboard/asrock/h77pro4-m/Kconfig
new file mode 100644
index 0000000000..50bf86c9db
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/Kconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if BOARD_ASROCK_H77PRO4_M
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select DRIVERS_ASMEDIA_ASPM_BLACKLIST
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_C216
+	select SUPERIO_NUVOTON_NCT6776
+	select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+	default "asrock/h77pro4-m"
+
+config MAINBOARD_PART_NUMBER
+	default "H77 Pro4-M"
+
+endif
diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig.name b/src/mainboard/asrock/h77pro4-m/Kconfig.name
new file mode 100644
index 0000000000..03873b96f0
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASROCK_H77PRO4_M
+	bool "H77 Pro4-M"
diff --git a/src/mainboard/asrock/h77pro4-m/Makefile.inc b/src/mainboard/asrock/h77pro4-m/Makefile.inc
new file mode 100644
index 0000000000..a0d1155a9a
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asrock/h77pro4-m/acpi/ec.asl b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl
diff --git a/src/mainboard/asrock/h77pro4-m/acpi/platform.asl b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl
new file mode 100644
index 0000000000..146be6592e
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/asrock/h77pro4-m/acpi/superio.asl b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asrock/h77pro4-m/board_info.txt b/src/mainboard/asrock/h77pro4-m/board_info.txt
new file mode 100644
index 0000000000..5f86088de5
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asrock.com/mb/Intel/H77%20Pro4-M/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/asrock/h77pro4-m/cmos.default b/src/mainboard/asrock/h77pro4-m/cmos.default
new file mode 100644
index 0000000000..23386fb6d3
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
+cpu_fan_tach_src=CPU_FAN1
diff --git a/src/mainboard/asrock/h77pro4-m/cmos.layout b/src/mainboard/asrock/h77pro4-m/cmos.layout
new file mode 100644
index 0000000000..ac88ee9621
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/cmos.layout
@@ -0,0 +1,96 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+
+409	2	e	4	power_on_after_fail
+411	2	e	5	sata_mode
+
+# coreboot config options: northbridge
+416	5	e	6	gfx_uma_size
+
+# coreboot config options: mainboard-specific
+421	2	e	7	cpu_fan_tach_src
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID	value	text
+
+# Generic on/off enum
+1	0	Disable
+1	1	Enable
+
+# boot_option
+2	0	Fallback
+2	1	Normal
+
+# debug_level
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+# power_on_after_fail
+4	0	Disable
+4	1	Enable
+4	2	Keep
+
+# sata_mode
+5	0	AHCI
+5	1	Compatible
+5	2	Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6	0	32M
+6	1	64M
+6	2	96M
+6	3	128M
+6	4	160M
+6	5	192M
+6	6	224M
+6	7	256M
+6	8	288M
+6	9	320M
+6	10	352M
+6	11	384M
+6	12	416M
+6	13	448M
+6	14	480M
+6	15	512M
+6	16	1024M
+
+# cpu_fan_header (select which header provides the tachometer
+# signal to the Super I/O on its CPUFANIN input)
+7	0	None
+7	1	CPU_FAN1
+7	2	CPU_FAN2
+7	3	Both
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/asrock/h77pro4-m/data.vbt b/src/mainboard/asrock/h77pro4-m/data.vbt
new file mode 100644
index 0000000000..52a8268f33
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/data.vbt
diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb
new file mode 100644
index 0000000000..86468c1e54
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device cpu_cluster 0 on
+		chip cpu/intel/model_206ax
+			register "acpi_c1" = "1"
+			register "acpi_c2" = "3"
+			register "acpi_c3" = "5"
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x1849 0x0100
+		end
+		device pci 01.0 on end # PEG - slot "PCIE1"
+		device pci 02.0 on # iGPU
+			subsystemid 0x1849 0x0102
+		end
+		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+			register "gen1_dec" = "0x000c0291"
+			register "gen2_dec" = "0x000c0241"
+			register "gen3_dec" = "0x000c0251"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3f"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+			register "superspeed_capable_ports" = "0x0000000f"
+			register "xhci_overcurrent_mapping" = "0x00000c03"
+			register "xhci_switchable_ports" = "0x0000000f"
+			device pci 14.0 on # USB 3.0 Controller
+				subsystemid 0x1849 0x1e31
+			end
+			device pci 16.0 on # Management Engine Interface 1
+				subsystemid 0x1849 0x1e3a
+			end
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on # USB2 EHCI #2
+				subsystemid 0x1849 0x1e2d
+			end
+			device pci 1b.0 on # High Definition Audio
+				subsystemid 0x1849 0x8892
+			end
+			device pci 1c.0 on # PCIe Port #1 - slot "PCIE4", 4 lanes
+				subsystemid 0x1849 0x1e10
+			end
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 on # PCIe Port #5 - slot "PCIE2", 1 lane
+				subsystemid 0x1849 0x1e18
+			end
+			device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE
+				subsystemid 0x1849 0x1e1a
+			end
+			device pci 1c.6 on # PCIe Port #7 - slot "PCIE3", 1 lane
+				subsystemid 0x1849 0x1e16
+			end
+			device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller
+				subsystemid 0x1849 0x1e1e
+			end
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x1849 0x1e26
+			end
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on # LPC bridge
+				subsystemid 0x1849 0x1e4a
+				chip superio/nuvoton/nct6776
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.1 on		# Parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 5
+						drq 0x74 = 3
+					end
+					device pnp 2e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM2, IR
+					device pnp 2e.5 on		# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off end		# CIR
+					device pnp 2e.7   off end	# GPIO8
+					device pnp 2e.107 off end	# GPIO9
+					device pnp 2e.8 off end		# WDT1
+					device pnp 2e.108 off end	# GPIO0
+					device pnp 2e.208 off end	# GPIOA
+					device pnp 2e.308 on		# GPIO base
+						io 0x60 = 0x0
+						irq 0xf0 = 0x3e		# + GPIO1 direction
+						irq 0xf1 = 0xde		# + GPIO1 value
+					end
+					device pnp 2e.109 on end	# GPIO1
+					device pnp 2e.209 on		# GPIO2
+						irq 0xe0 = 0xff		# + GPIO2 direction
+						irq 0xe1 = 0x0c		# + GPIO2 value
+					end
+					device pnp 2e.309 on		# GPIO3
+						irq 0xe4 = 0xf7		# + GPIO3 direction
+						irq 0xe5 = 0x08		# + GPIO3 value
+					end
+					device pnp 2e.409 off end	# GPIO4
+					device pnp 2e.509 off end	# GPIO5
+					device pnp 2e.609 off end	# GPIO6
+					device pnp 2e.709 on end	# GPIO7
+					device pnp 2e.a on		# ACPI
+						irq 0xe4 = 0x10 	# + enable 3VSBSW#
+						irq 0xf0 = 0x20 	# + pin 70 = 3VSBSW
+					end
+					device pnp 2e.b on		# HWM, front panel LED
+						irq 0x30 = 0xe1		# + Fan RPM sense pins
+						io  0x60 = 0x0290	# + HWM base address
+					end
+					device pnp 2e.d off end		# VID
+					device pnp 2e.e off end		# CIR WAKE-UP
+					device pnp 2e.f off end		# GPIO Push-Pull or Open-drain
+					device pnp 2e.14 off end	# SVID
+					device pnp 2e.16 off end	# Deep Sleep
+					device pnp 2e.17 off end	# GPIOA
+				end
+			end
+			device pci 1f.2 on # SATA (AHCI)
+				subsystemid 0x1849 0x1e02
+			end
+			device pci 1f.3 on # SMBus
+				subsystemid 0x1849 0x1e22
+			end
+			device pci 1f.5 off end # SATA (Legacy)
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/asrock/h77pro4-m/dsdt.asl b/src/mainboard/asrock/h77pro4-m/dsdt.asl
new file mode 100644
index 0000000000..33cd0e5d0b
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c
new file mode 100644
index 0000000000..48024cba5c
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/early_init.c
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <option.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define GLOBAL_DEV   PNP_DEV(0x2e, 0)
+#define SERIAL_DEV   PNP_DEV(0x2e, NCT6776_SP1)
+#define GPIO6789_DEV PNP_DEV(0x2e, NCT6776_GPIO6789_V)
+
+/* As defined in cmos.layout */
+enum cpu_fan_tach_src {
+	CPU_FAN_HEADER_NONE,
+	CPU_FAN_HEADER_1,
+	CPU_FAN_HEADER_2,
+	CPU_FAN_HEADER_BOTH
+};
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 1, 1 },
+	{ 1, 1, 1 },
+	{ 1, 1, 2 },
+	{ 1, 1, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 1, 5 },
+	{ 1, 1, 5 },
+	{ 1, 0, 6 },
+};
+
+/*
+ * The tachometer signal that goes to CPUFANIN of the Super I/O is set via
+ * GPIOs.
+ *
+ * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected.
+ * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected.
+ * When both are '0' and both fans are connected, wrong readings will
+ * be reported.
+ */
+static u8 get_cpufanin_gpio_config(void)
+{
+	switch (get_uint_option("cpu_fan_tach_src", CPU_FAN_HEADER_1)) {
+	case CPU_FAN_HEADER_NONE:
+		return 0xff;
+	case CPU_FAN_HEADER_1:
+	default:
+		return 0x7f;
+	case CPU_FAN_HEADER_2:
+		return 0xbf;
+	case CPU_FAN_HEADER_BOTH:
+		return 0x3f;
+	}
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Configure Super I/O pins */
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0x68);
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x80);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0x5c);
+	pnp_write_config(GLOBAL_DEV, 0x27, 0xc0);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x62);
+	pnp_write_config(GLOBAL_DEV, 0x2b, 0x08);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
+
+	/* GP77 and GP76 are outputs. They set the tachometer input on CPUFANIN. */
+	pnp_set_logical_device(GPIO6789_DEV);
+	pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f);
+	pnp_write_config(GPIO6789_DEV, 0xe1, get_cpufanin_gpio_config());
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	/* Enable UART */
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads
new file mode 100644
index 0000000000..b05255dea2
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1,  -- DVI-D connector
+      HDMI3,  -- HDMI connector
+      Analog, -- D-Sub connector
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asrock/h77pro4-m/gpio.c b/src/mainboard/asrock/h77pro4-m/gpio.c
new file mode 100644
index 0000000000..84f4564fff
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/gpio.c
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_NATIVE,
+	.gpio39 = GPIO_MODE_NATIVE,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_NATIVE,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c
new file mode 100644
index 0000000000..51133e7c7c
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0892,	/* Codec Vendor / Device ID: Realtek ALC892 */
+	0x18498892,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x18498892),
+	AZALIA_PIN_CFG(0, 0x11, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19950),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214120),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+	0x80862806,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;