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authorElyes Haouas <ehaouas@noos.fr>2022-11-29 17:36:51 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-12-02 14:39:56 +0000
commitdc3beea75d3050600842112cfd7fd48baa65278d (patch)
treeca9839a61c90cc7b972650c0eb1a2e92a6a25eb9 /src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
parent87a98b55b2466638587ea44fc7eaa13d93525656 (diff)
sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb')
-rw-r--r--src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
index e0df76be96..23268f2bdf 100644
--- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
@@ -33,7 +33,7 @@ chip northbridge/intel/x4x # Northbridge
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1"
+ register "ide_enable_primary" = "true"
register "gpe0_en" = "0x440"
register "gen1_dec" = "0x000c0291" # Superio HWM