From dc3beea75d3050600842112cfd7fd48baa65278d Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Tue, 29 Nov 2022 17:36:51 +0100 Subject: sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary} Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb') diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index e0df76be96..23268f2bdf 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/intel/x4x # Northbridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" register "gen1_dec" = "0x000c0291" # Superio HWM -- cgit v1.2.3