diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-10 23:13:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-06 10:38:22 +0000 |
| commit | 5eb81bed2ea503aaf910430da492ed75d27ef94f (patch) | |
| tree | 562c5611149b81c7b81d96c242feff2fe3dede78 /src/mainboard/asrock/g41c-gs/variants/g41m-gs | |
| parent | fefe7afeb0abb9d779f1e3b025dde6e1164dac9d (diff) | |
sb/intel/i82801gx: Detect if the southbridge supports AHCI
This automatically detects whether the southbridge supports AHCI.
If AHCI support is selected it will be used unless "sata_no_ahci" is
set in the devicetree to override the behavior.
Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs/variants/g41m-gs')
| -rw-r--r-- | src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index ba2f00d1ec..f4d1dc4291 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -46,7 +46,6 @@ chip northbridge/intel/x4x # Northbridge register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" |