From 5eb81bed2ea503aaf910430da492ed75d27ef94f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 10 Jan 2019 23:13:11 +0100 Subject: sb/intel/i82801gx: Detect if the southbridge supports AHCI This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/asrock/g41c-gs/variants/g41m-gs') diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index ba2f00d1ec..f4d1dc4291 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -46,7 +46,6 @@ chip northbridge/intel/x4x # Northbridge register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" -- cgit v1.2.3