diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-11 12:09:28 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-06 18:39:22 +0200 |
| commit | 59a4cd55782f1148d37f0c2408657ba93deefc86 (patch) | |
| tree | ec8afec917b945d042b753a4043219a49798bb0c /src/mainboard/asrock/e350m1/agesawrapper.h | |
| parent | 997d25219b67704ba497a3d67f392a8a743a1782 (diff) | |
baytrail: add support for routing gpio pins to smi/sci
In order for gpio pins to trigger an smi/sci the GPIO_ROUT
register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
register needs to be enabled for each gpio as well.
The first 8 gpios from the suspend and core well are the only gpios
that can trigger an SMI or SCI. The settings for the GPIO_ROUT
and ALT_GPIO_SMI register are not commited until the SMM settings
are enabled in the southcluster.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
and toggling PCH_WAKE_L on the EC console.
Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176390
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4957
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/asrock/e350m1/agesawrapper.h')
0 files changed, 0 insertions, 0 deletions