diff options
| author | Dave Frodin <dave.frodin@se-eng.com> | 2015-01-19 11:40:38 -0700 |
|---|---|---|
| committer | Dave Frodin <dave.frodin@se-eng.com> | 2015-01-27 15:07:45 +0100 |
| commit | bc21a41e1ca045baae57f79d89aafdf682528a4b (patch) | |
| tree | 217891284eb2f483f57a053b94d1f4fc6e7f94fe /src/mainboard/amd/olivehillplus/dsdt.asl | |
| parent | bd1d1580d3cdbd1f438e8fb0d960102f252c6939 (diff) | |
southbridge/amd/pi: Rename Avalon to Hudson
To maintain consistancy with southbridge/amd/agesa/hudson rename
pi/avalon to pi/hudson in advance of adding support for the
base hudson southbridge.
Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8251
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/amd/olivehillplus/dsdt.asl')
| -rw-r--r-- | src/mainboard/amd/olivehillplus/dsdt.asl | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl index 56381e18f3..68ed74e84a 100644 --- a/src/mainboard/amd/olivehillplus/dsdt.asl +++ b/src/mainboard/amd/olivehillplus/dsdt.asl @@ -37,13 +37,13 @@ DefinitionBlock ( #include "acpi/usb_oc.asl" /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/pi/avalon/acpi/pcie.asl> + #include <southbridge/amd/pi/hudson/acpi/pcie.asl> /* Describe the processor tree (\_PR) */ #include <cpu/amd/pi/00730F01/acpi/cpu.asl> /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/pi/avalon/acpi/sleepstates.asl> + #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl> /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ #include "acpi/sleep.asl" @@ -68,16 +68,16 @@ DefinitionBlock ( #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/pi/avalon/acpi/fch.asl> + #include <southbridge/amd/pi/hudson/acpi/fch.asl> } /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/pi/avalon/acpi/pci_int.asl> + #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/pi/avalon/acpi/smbus.asl> + #include <southbridge/amd/pi/hudson/acpi/smbus.asl> /* Define the General Purpose Events for the platform */ #include "acpi/gpe.asl" |