From bc21a41e1ca045baae57f79d89aafdf682528a4b Mon Sep 17 00:00:00 2001 From: Dave Frodin Date: Mon, 19 Jan 2015 11:40:38 -0700 Subject: southbridge/amd/pi: Rename Avalon to Hudson To maintain consistancy with southbridge/amd/agesa/hudson rename pi/avalon to pi/hudson in advance of adding support for the base hudson southbridge. Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3 Signed-off-by: Dave Frodin Reviewed-on: http://review.coreboot.org/8251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/mainboard/amd/olivehillplus/dsdt.asl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mainboard/amd/olivehillplus/dsdt.asl') diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl index 56381e18f3..68ed74e84a 100644 --- a/src/mainboard/amd/olivehillplus/dsdt.asl +++ b/src/mainboard/amd/olivehillplus/dsdt.asl @@ -37,13 +37,13 @@ DefinitionBlock ( #include "acpi/usb_oc.asl" /* PCI IRQ mapping for the Southbridge */ - #include + #include /* Describe the processor tree (\_PR) */ #include /* Contains the supported sleep states for this chipset */ - #include + #include /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ #include "acpi/sleep.asl" @@ -68,16 +68,16 @@ DefinitionBlock ( #include /* Describe the AMD Fusion Controller Hub Southbridge */ - #include + #include } /* Describe PCI INT[A-H] for the Southbridge */ - #include + #include } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */ - #include + #include /* Define the General Purpose Events for the platform */ #include "acpi/gpe.asl" -- cgit v1.2.3