diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-07 17:32:50 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-10 17:13:14 +0200 |
| commit | 6ed319a796b646894892e70a5757df84efea5785 (patch) | |
| tree | a53091e674fcef89936bba2b5c4bfc40af90eb00 /src/mainboard/advansus/a785e-i/romstage.c | |
| parent | 023e284a068ee19a4447b70a67e1ccfadadbeca9 (diff) | |
mainboard/advansus: Use C89 comments style & remove commented code
Change-Id: Ib44bc66e02901dbde14361091a049f71c3ecb840
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16921
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Diffstat (limited to 'src/mainboard/advansus/a785e-i/romstage.c')
| -rw-r--r-- | src/mainboard/advansus/a785e-i/romstage.c | 34 |
1 files changed, 8 insertions, 26 deletions
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 45e5d50e3b..c067664562 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ +#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -86,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - //enable port80 decoding and southbridge poweron init + /* enable port80 decoding and southbridge poweron init */ sb_Poweron_Init(); } @@ -108,12 +106,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); printk(BIOS_DEBUG, "\n"); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +162,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +192,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,23 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** |