diff options
| -rw-r--r-- | src/mainboard/advansus/a785e-i/platform_cfg.h | 2 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/resourcemap.c | 10 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/romstage.c | 34 |
3 files changed, 11 insertions, 35 deletions
diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index 5e93dc1934..3f31f9f19c 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -161,7 +160,6 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/advansus/a785e-i/resourcemap.c b/src/mainboard/advansus/a785e-i/resourcemap.c index 2978bab7a9..4f2c074bd6 100644 --- a/src/mainboard/advansus/a785e-i/resourcemap.c +++ b/src/mainboard/advansus/a785e-i/resourcemap.c @@ -43,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -81,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -129,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -191,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -221,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -262,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 45e5d50e3b..c067664562 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ +#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -86,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - //enable port80 decoding and southbridge poweron init + /* enable port80 decoding and southbridge poweron init */ sb_Poweron_Init(); } @@ -108,12 +106,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); printk(BIOS_DEBUG, "\n"); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +162,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +192,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,23 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** |