diff options
| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2024-10-29 09:13:30 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-08 19:09:55 +0000 |
| commit | 89e6640bf911b607bb169984ee5f20be352d79fa (patch) | |
| tree | 29068b37faf2def5856dedd5556ebb4ad13e1c64 /src/include | |
| parent | 84527cbb9676bda60fad7448f1ecad50afb98f12 (diff) | |
device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0
This patch adds new DID0 PCI device IDs for Intel PTL-H.
Additionally, updates the System Agent driver's `systemagent_ids`
list and Panther Lake SoC bootblock to support these new IDs.
Source: Intel PTL-FAS. Document Number 812562
BUG=b:347669091
TEST=Build fatcat and boot with Panther Lake SoC with newly added
MCH ID.
With patch, coreboot log:
`[DEBUG] MCH: device id b004 (rev 00) is Pantherlake H`
`[DEBUG] MCH: device id b00a (rev 00) is Pantherlake H`
Change-Id: I56e795696f661d88828d7549f856eee19c46c942
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84916
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4730f3f2d9..638689144d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4456,6 +4456,8 @@ #define PCI_DID_INTEL_PTL_U_ID_1 0xb000 #define PCI_DID_INTEL_PTL_H_ID_1 0xb001 #define PCI_DID_INTEL_PTL_H_ID_2 0xb002 +#define PCI_DID_INTEL_PTL_H_ID_3 0xb004 +#define PCI_DID_INTEL_PTL_H_ID_4 0xb00a #define PCI_DID_INTEL_SNR_ID 0x09a2 /* Intel SMBUS device Ids */ |