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authorRavi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>2022-10-11 23:54:55 -0700
committerSubrata Banik <subratabanik@google.com>2022-11-15 10:46:21 +0000
commit33005df7bcc63550955986f8f6714c595b3b8d70 (patch)
treec25cce3656d1179230f24a7cc2e100f1ac76fa77 /src/include
parentf2e2dc80fa68facbce14d06aa111ca8ab4529bbe (diff)
soc/intel: Add Meteor Lake IGD device id 0x7d45
Add new IGD device. Reference: EDS Vol 1 (640228) Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 949afbdd90..5e270cec1f 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4001,9 +4001,10 @@
#define PCI_DID_INTEL_ADL_N_GT2 0x46D1
#define PCI_DID_INTEL_ADL_N_GT3 0x46D2
#define PCI_DID_INTEL_MTL_M_GT2 0x7d40
-#define PCI_DID_INTEL_MTL_P_GT2_1 0x7d50
-#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d55
-#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d60
+#define PCI_DID_INTEL_MTL_P_GT2_1 0x7d45
+#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50
+#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55
+#define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60
#define PCI_DID_INTEL_RPL_P_GT1 0xa720
#define PCI_DID_INTEL_RPL_P_GT2 0xa7a8
#define PCI_DID_INTEL_RPL_P_GT3 0xa7a0