diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2020-01-08 15:22:13 -0800 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-18 12:03:17 +0000 |
| commit | 39e1f44f331040b2e9574e9c792f583b8c6a5aba (patch) | |
| tree | 96b3a479ae3107442e01c612eaf588dee0759daa /src/include/device/pci_ids.h | |
| parent | 06a078a06723ec5c085b6a8df3adee98e6171b5f (diff) | |
soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for
10-Core ID.
Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6c3c2980d1..59a3883ec7 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3399,9 +3399,11 @@ #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 #define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 #define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 -#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53 -#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B33 #define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_4 0x9B63 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_2 0x9B73 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 |