From 39e1f44f331040b2e9574e9c792f583b8c6a5aba Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Wed, 8 Jan 2020 15:22:13 -0800 Subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for 10-Core ID. Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/include/device/pci_ids.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/include/device/pci_ids.h') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6c3c2980d1..59a3883ec7 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3399,9 +3399,11 @@ #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 #define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 #define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 -#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53 -#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B33 #define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_4 0x9B63 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_2 0x9B73 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 -- cgit v1.2.3