diff options
author | Reka Norman <rekanorman@google.com> | 2022-09-27 16:08:08 +1000 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-30 13:19:05 +0000 |
commit | d9cb72559fa0f6251cc5144688da762daca1205f (patch) | |
tree | 23df5a1f4621a23cdc58711ac75df840b19f7336 /src/include/bootstate.h | |
parent | a88d5e3bcafdbc8d2cc2491a04de839eef4f6a4e (diff) |
mb/google/nissa: Change TPM I2C freqeuncy to 1 MHz
Change the TPM I2C freqeuncy to 1 MHz for nivviks and nereid, and in
the baseboard. Other nissa devices will be changed after verification.
This saves 11 ms of boot time on nivviks and nereid.
400 kHz:
504:finished TPM initialization 272,304 (35,730)
...
512:finished TPM PCR extend 526,250 (23,729)
513:starting locking TPM 526,250 (0)
514:finished locking TPM 535,106 (8,855)
6:end of verified boot 543,927 (8,821)
1 MHz:
504:finished TPM initialization 266,293 (30,747)
...
512:finished TPM PCR extend 513,711 (20,108)
513:starting locking TPM 513,711 (0)
514:finished locking TPM 521,311 (7,599)
6:end of verified boot 528,893 (7,581)
BUG=b:249201598
TEST=On nivviks and nereid, all timing requirements in the spec are met.
Frequencies:
nivviks - 972.01 kHz
nereid - 968.99 kHz
Change-Id: I9dd783527d4215ed7d79d69853a1f321ea2d8a28
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/include/bootstate.h')
0 files changed, 0 insertions, 0 deletions