diff options
| author | Reka Norman <rekanorman@google.com> | 2022-09-27 16:08:08 +1000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-30 13:19:05 +0000 |
| commit | d9cb72559fa0f6251cc5144688da762daca1205f (patch) | |
| tree | 23df5a1f4621a23cdc58711ac75df840b19f7336 | |
| parent | a88d5e3bcafdbc8d2cc2491a04de839eef4f6a4e (diff) | |
mb/google/nissa: Change TPM I2C freqeuncy to 1 MHz
Change the TPM I2C freqeuncy to 1 MHz for nivviks and nereid, and in
the baseboard. Other nissa devices will be changed after verification.
This saves 11 ms of boot time on nivviks and nereid.
400 kHz:
504:finished TPM initialization 272,304 (35,730)
...
512:finished TPM PCR extend 526,250 (23,729)
513:starting locking TPM 526,250 (0)
514:finished locking TPM 535,106 (8,855)
6:end of verified boot 543,927 (8,821)
1 MHz:
504:finished TPM initialization 266,293 (30,747)
...
512:finished TPM PCR extend 513,711 (20,108)
513:starting locking TPM 513,711 (0)
514:finished locking TPM 521,311 (7,599)
6:end of verified boot 528,893 (7,581)
BUG=b:249201598
TEST=On nivviks and nereid, all timing requirements in the spec are met.
Frequencies:
nivviks - 972.01 kHz
nereid - 968.99 kHz
Change-Id: I9dd783527d4215ed7d79d69853a1f321ea2d8a28
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
3 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 56b1ded3b5..d002db6394 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -102,11 +102,11 @@ chip soc/intel/alderlake register "common_soc_config" = "{ .i2c[0] = { .early_init = 1, - .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_FAST_PLUS, .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 158, - .scl_hcnt = 79, + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, .sda_hold = 7, } }, diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index b2ada07e6d..4baca1dac0 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -50,11 +50,11 @@ chip soc/intel/alderlake register "common_soc_config" = "{ .i2c[0] = { .early_init = 1, - .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_FAST_PLUS, .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 158, - .scl_hcnt = 79, + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, .sda_hold = 7, } }, diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index f8c5ef45b8..76fe43e71c 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -72,11 +72,11 @@ chip soc/intel/alderlake register "common_soc_config" = "{ .i2c[0] = { .early_init = 1, - .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_FAST_PLUS, .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 160, - .scl_hcnt = 79, + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, .sda_hold = 7, } }, |