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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-07 15:07:46 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-12 20:45:52 +0000 |
| commit | 79e61603dc1e7c335a3e3f9c1f70b135cd8cfb96 (patch) | |
| tree | e50e09e41b8b988b75dfaf1715d564f56a9137e6 /src/include/bootsplash.h | |
| parent | a3cd3066ba8176b61a0ae917105bf13b513232fa (diff) | |
soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
PCH-S maps certain MMIO BARs differently than low power PCHs. The
reserved ranges taken from Intel DOC #630603.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include/bootsplash.h')
0 files changed, 0 insertions, 0 deletions